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Description: c++书写的互联网缓存模拟器，可用来方便相关的研究工作-c writing Internet cache simulator can be used to facilitate the research work
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Size: 22429 |
Author: 丁丁 |
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Description: c++书写的互联网缓存模拟器，可用来方便相关的研究工作-c writing Internet cache simulator can be used to facilitate the research work
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Size: 22528 |
Author: 丁丁 |
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Description: 这是个trace drive的Cache模拟器，可以在window和linux下编译运行，是做体系结构研究的好帮手-This is a trace drive the Cache Simulator, you can compile window and run under linux, is to do Research on Architecture of a good helper
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Size: 295936 |
Author: suoguang |
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Description: 一个很有名的硬件模拟器。可以模拟CPU，cache，以及内存等。支持多核处理器的模拟。-A well-known hardware simulator. Can simulate the CPU, cache, and memory. Support multi-core processor simulation.
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Size: 4423680 |
Author: 雷田 |
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Description: The DHRY program performs the dhrystone benchmarks on the 8051.
Dhrystone is a general-performance benchmark test originally
developed by Reinhold Weicker in 1984. This benchmark is
used to measure and compare the performance of different
computers or, in this case, the efficiency of the code
generated for the same computer by different compilers.
The test reports general performance in dhrystones per second.
Like most benchmark programs, dhrystone consists of standard
code and concentrates on string handling. It uses no
floating-point operations. It is heavily influenced by
hardware and software design, compiler and linker options,
code optimizing, cache memory, wait states, and integer
data types.
The DHRY program is available in different targets:
Simulator: Large Model: DHRY example in LARGE model
for Simulation
Philips 80C51MX: DHRY example in LARGE model
for the Philips 80C51MC
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Size: 23552 |
Author: aglo |
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Description: 用C语言来实现虚拟cache的操作，加深对CACHE的理解-I extend a cache simulator with a simulator of a victim cache. First I describe what a victim cache is. After that, i describe the cache simulator and present the assignment.
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Size: 35840 |
Author: zy |
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Description: spim-cache 模 拟 器 安 装 程 序-spim-cache simulator setup
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Size: 55296 |
Author: |
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Description: It is a cache simulator for L1 and L2
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Size: 1024 |
Author: Hassan |
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Description: 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.
The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.
The simulator exhibits performance over 500 K instructions/sec, which is fairly high for a cycle-accurate system-level simulator.
The simulator’s source co
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Size: 4886528 |
Author: Archie |
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Description: Cache Simulator implementing block placement and update policy
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Size: 850944 |
Author: Vijay |
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Description: Simulates a cache simulator Computer Architecture.
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Size: 377856 |
Author: zedd |
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Description: 缓存模拟
The cache simulator uses the 16-bit memory address and can be configured to simulate various types of cache design characterized with three parameters: the cache size, the block size, and the set
associativity-cache simulator
The cache
simulator uses the 16-bit memory address and can be configured to simulate various types of cache design characterized with three parameters: the cache size, the block size, and the set
associativity
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Size: 135168 |
Author: Yan Liu |
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Description: Cache simulator that for any given configuration of direct/associative caches calculates number of hits/misses!
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Size: 3072 |
Author: amitabhh |
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Description: 一个cache模拟器，根据一串输入来输出hit数与miss数-a cache simulator
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Size: 1024 |
Author: sillykid |
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Description: cache 模拟器：支持LRU和random两种替换策略-cache simulator: support LRU and random replacement strategies
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Size: 2048 |
Author: luluxiu |
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Description: 可视化Cache模拟器，实现了多种功能，可选择写回/不写回、LRU/FIFO/RAND，直写/写缓存等方式-An visiable Cache simulator
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Size: 3059712 |
Author: yuzhuolong |
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Description: 使用Qt实现的多cache一致性模拟器，该模拟器采用监听协议。模拟对象为多处理器，多cache,集中共享式存储器条件下cache数据的一致性。-Use Qt achieve more consistency cache simulator, the simulator uses protocol listeners. Mock objects for multi-processor, multi-cache, consistency conditions under centralized shared memory cache data.
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Size: 12288 |
Author: 曹欣 |
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Description: VS2010环境下编写的cache模拟器，可以设置cache容量，cache块的大小，选择映射方法，计算不命中率，输入文件格式为地址流文件，模拟存储器。-VS2010 environment write cache simulator, you can set the cache capacity, the size of the cache block, the mapping method, the calculation does not hit rate, the input file stream file format for addresses, analog memory.
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Size: 9216 |
Author: 曹欣 |
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Description: 64K 4路 组相连 随机替换 cache 模拟程序-64K random replacement set-associative cache simulator
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Size: 2048 |
Author: 李文明 |
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Description: 性能分析以及cache模拟器编程，实现写策略，读策略，替换策略等-Performance analysis and cache simulator programming
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Size: 3072 |
Author: bff |
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