Welcome![Sign In][Sign Up]
Location:
Search - cadence virtuoso

Search list

[Other resourcementor

Description: Cadence设计系统公司(纽约证券交易所代码:CDN)和广晟微电子公司今天共同宣布,广晟已经通过Cadence Virtuoso 全定制平台成功地开发出第一代10Gbps高速光传输集成电路(IC),而且只用了不到16个星期的时间。借助Virtuoso全定制设计平台为先进的全定制IC设计提供的整合平台、完整流程以及最优化的技术,广晟无需进行硅反复设计即可制作出复杂的通讯用集成电路。
Platform: | Size: 3719175 | Author: 谢峰 | Hits:

[Bookscadence

Description: cadence教程。内容全面,各种检证方法详细列举。适合各种层次的学习者。-cadence tutorial. Comprehensive range of inspection methods in detail. Suitable for all levels of learners.
Platform: | Size: 1673216 | Author: luo | Hits:

[Software Engineeringmentor

Description: Cadence设计系统公司(纽约证券交易所代码:CDN)和广晟微电子公司今天共同宣布,广晟已经通过Cadence Virtuoso 全定制平台成功地开发出第一代10Gbps高速光传输集成电路(IC),而且只用了不到16个星期的时间。借助Virtuoso全定制设计平台为先进的全定制IC设计提供的整合平台、完整流程以及最优化的技术,广晟无需进行硅反复设计即可制作出复杂的通讯用集成电路。 -Cadence Design Systems, Inc. (NYSE: CDN) and Rising Micro Electronics Corporation today announced that Rising has adopted Cadence Virtuoso Custom Platform successfully developed the first-generation 10Gbps optical transmission of high-speed integrated circuits (IC), and only less than 16 weeks time. With Virtuoso Custom Design Platform for advanced full-custom IC design platform to provide integrated, complete and optimize the flow of technology, widely sung repeatedly the need for the design of silicon can produce complex integrated circuits for communications.
Platform: | Size: 3719168 | Author: 谢峰 | Hits:

[OtherCadence_MEDICI

Description: 本手册共分为三部分:第一部分分为四章,分别介绍Cadence cdsSpice、virtuoso Editing、Diva和verilog。第二部分主要介绍MEDICI。第三部分是附录部分,是对前两章的一个补充,并简要的介绍了寄生元件提取语句的语法。-This manual is divided into three parts: the first part is divided into four chapters, respectively, introduce Cadence cdsSpice, virtuoso Editing, Diva and verilog. Introduce the second part of the main MEDICI. The third part is the appendix of the first two chapters of a supplement to, and briefly introduce the components of the parasitic extraction statement grammar.
Platform: | Size: 16741376 | Author: zjh | Hits:

[Other systemsCalculateWL

Description: 计算电路中晶体管的关键参数。 界面友好,功能实用。-a useful tools to calculate the scale of mos transistor. This Program is dedicated to calculate the Parameters of the MOSFET in analog IC design. Microsoft .net framework 2.0 or above is needed. 1) Input every THREE parameters in (Ids, Vdsat, Vds, W/L) to claculate the other one. Leave the textbox of the parameter to be calculated in EMPTY. 2) Input the ABS value of Ids, Vdsat and Vds for pmos. 3) Fast Switch: Use space, enter or tab to switch to the next input area quickly. 4) Dynamic Increase: Press the button "+" to increase the number of MOSFET. 5) Program can minizied to system tray. Click to bring it to front. 6) Select "On Top" when you finished calculation and intput data in other programs like Cadence Virtuoso.
Platform: | Size: 14336 | Author: 杜睿 | Hits:

[OtherVirtuoso-XL_Layout_Editor

Description: Virtuoso-XL_Layout_Editor best free cadence tutorial material guide in design asic and soc
Platform: | Size: 2922496 | Author: loktikvj | Hits:

[Otherbus

Description: 在cadence virtuoso 下画bus的skill程序。-In the cadence virtuoso painting under the bus of the skill procedure.
Platform: | Size: 1024 | Author: cgqiao | Hits:

[OtheralignObj

Description: 在cadence virtuoso 下自动对齐已选中的layout-In the cadence virtuoso, automatic alignment has been selected layout
Platform: | Size: 4096 | Author: cgqiao | Hits:

[Otherchlib

Description: 在cadence virtuoso schematic 自动替换已有的cell到不同的lib-In the cadence virtuoso schematic automatically replace the existing cell to a different lib
Platform: | Size: 7168 | Author: cgqiao | Hits:

[OtherspHiCreateMultiLabel

Description: 在cadence virtuoso layout下可以自动/手动打label-In the cadence virtuoso layout may be automatic/manual beat label
Platform: | Size: 2048 | Author: cgqiao | Hits:

[OtherTap_MPP

Description: 在cadence virtuoso layout下画tap的程序-In the cadence virtuoso layout program under the painted tap
Platform: | Size: 4096 | Author: cgqiao | Hits:

[Linux-UnixBinKeys

Description: layout时有西功能没有快捷键,以下脚本就增加一些好用的功能的快捷方式,可更改。-add Cadence virtuoso ShortKey
Platform: | Size: 1024 | Author: chenyugu | Hits:

[Otherdeletevia

Description: 删除孤立过孔,cadence skill开发的程序-delete via
Platform: | Size: 2048 | Author: oday | Hits:

[Othervirtuoso_skill_code

Description: 用于 cadence virtuoso的skill代码 CCStoggleLayerSel.il 选择LSW对应层上的所有图形 coord.il 得到选择obj的坐标并输出 dataBrowser.il 显示cellview的所有数据 doublesel.il 选择与当前选择的obj相同的其它obj objinfo.il 在virtuoso界面显示鼠标点击选择obj的信息,如W L,面积,Layer,网线名称 Path_Length.il 计算path的长度 PutOnGrid.il 修改格点问题,可能会出现错位 setCellLayerValid.il LSW显示当前cell里所用到的所有层 showLayer.il 显示当前cell所用到的层 showlib.il 显示library sigwidth.il 得到width并输出 spHiCreateMultiLabel.il 创建多个label F3 symbolinfo.il 得到symbol的info并输出 Tap_Mpp.il 简单定义Guard_ring (使用 MultiPart Path)-Used for cad ence virtuoso environment of some of the skill code CCStoggleLayerSel. Il LSW choose corresponding levels all graphics Coord. Il get obj and output the coordinates of choice DataBrowser. Il shows cellview all of the data Doublesel. Il choice and the currently selected obj the same other obj Objinfo. Il in the virtuoso interface display the mouse to click the choice obj information, such as W L, area, Layer, string name Path_Length. Il calculation of the length of the path PutOnGrid. Il modify lattice point is the problem that there might be a dislocation SetCellLayerValid. Il LSW display the current cell used in all layers ShowLayer. Il show the current use cell layer Showlib. Il shows everyday Sigwidth. Il get width and output SpHiCreateMultiLabel. Il create multiple label F3 Symbolinfo. Il get symbol of info and output Tap_Mpp. Il simple definition Guard_ring (use MultiPart Path)
Platform: | Size: 19456 | Author: stokley | Hits:

[OtherIC-Backend-Design

Description: 集成电路的后端设计包括版图设计和验证。采用Cadence的Virtuoso Layout Editor的版图设计环境进行版图设计。利用Virtuoso Layout Editer的集成验证工具DIVA进行了验证。验证的整个的过程包括:设计规则检查(Design Rule Checking 简称DRC )、电学规则检查(Electronics Rule Checking 简称ERC)、电路图版图对照(Layout Versus Schematic 简称LVS)、以及版图寄生参数提取(Layout Parameter Extraction 简称LPE)-The integrated circuit the backend design including layout design and verification. Layout using Cadence Virtuoso Layout Editor environment for layout design. Integrated verification tools using Virtuoso Layout Editer DIVA verified. Verification of the entire process, including: design rule checking (Design Rule Checking DRC), electrical rule checking (Electronics Rule Checking ERC) Schematic layout control (Layout Versus Schematic LVS), and the layout parasitic extraction (Layout Parameter Extraction referred LPE)
Platform: | Size: 149504 | Author: alan | Hits:

[Otherchrt35dg_SiGe

Description: cadence virtuoso集成电路设计库,懂的人一定知道-cadence virtuoso
Platform: | Size: 2404352 | Author: higgsboson | Hits:

[OtherAdvanced-Analysis-Tools

Description: Cadence Virtuoso高级分析工具的使用说明,很详细-Advance Analyse Tools User Guide
Platform: | Size: 777216 | Author: xray | Hits:

[matlabVirtuosoToolbox

Description: cadence virtuoso 与matlab 交互的工具-matlab toolbox for cadence virtuoso
Platform: | Size: 74752 | Author: Xianliang Chen | Hits:

[Otherncsu-cdk-1.6.0.beta.tar

Description: NCSU PDK Technology Library for Cadence Virtuoso Work on Cadence IC 6.1 or higher
Platform: | Size: 3012608 | Author: ryulee88 | Hits:

[matlablossless

Description: matlab lossless algorithm
Platform: | Size: 27648 | Author: Ezhil | Hits:
« 12 »

CodeBus www.codebus.net