Search - convolution of 1D signal

Search - convolution of 1D signal - List

[DSP program] DSP-c-Matlab-Programs-ManualV19 DL : 0: 印度GURUNANAK ENGINEERING COLLEGE数字信号处理实验室的DSP+c+Matlab联合编程手册-DIGITAL SIGNAL PROCESSING LAB (IV-I SEM) INDEX 1. Architecture of DSP chips-TMS 320C 6713 DSP Processor 2. Linear convolution 3. Circular convolution 4. FIR Filter (LP/HP) Using Windowing technique a. Rectangular window b. Triangular window c. Kaiser window 5. IIR Filter(LP/HP) on DSP processors 6. N-point FFT algorithm 7. Power Spectral Density of a sinusoidal signals 8. FFT of 1-D signal plot 9. MATLAB program to generate sum of sinusoidal signals 10. MATLAB program to find frequency response of analog
Update : 2025-02-17 Size : 1.51mb Publisher : wangjin
[AI-NN-PR] CudaConv DL : 0: 功能还不大清楚，不是本人开发的-Convolution of an arbitrary 1D complex signal with an arbitrary filter kernel
Update : 2025-02-17 Size : 1kb Publisher : zhangqa
[matlab] CudaConv DL : 0: Convolution of an arbitrary 1D complex signal with an arbitrary filter kernel Author: Mario Tuerschmann please read the .txt files before using.
Update : 2025-02-17 Size : 2kb Publisher : hasan
[Other] A memory and area‑efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 D DL : 0: In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bitparallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations.
Update : 2021-10-05 Size : 3.28mb Publisher : nalevihtkas