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Description: 网络控制器和链路控制器的CPU即是通过读写双端口RAM芯片完成网络层与数据链路层的原语交互。mailbox中写入的是原语的类型，而双端口RAM的其它存储空间则存放各种服务原语的参数。-network controller and the CPU controller link is through reading and writing dual-port RAM chip to complete the network layer and data link layer of the original language interaction. Mailbox inclusion of the original language is the type of dual-port RAM and the other storage space incorporating various services parameters of the original language.
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Size: 1024 |
Author: 李历 |
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Description: C6713dsp to fpga dpram,自己调试成功了，交换万岁-C6713dsp to fpga dpram, debug their successful, long live exchange
Platform: |
Size: 2048 |
Author: 丁科 |
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Description:
Platform: |
Size: 130048 |
Author: sq |
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Description: verilog
功能：DSP或单片机向FPGA的DPRAM中写入一块数据（最大不超过2K字节,前2个字节为代发送数据长度），然后给出启动信号send_start，本模块自动读出DPRAM中的数据，按设定的波特率将DPRAM中规定的长度的数据发送出去。
接口信号说明：
send_start：启动FPGA串行发送脉冲
sys_rst：系统复位脉冲
bps_setup：波特率选择
clk5_714：5.714MHz时钟
char_in：从DPRAM中读出的代发送数据
ReadPtr_w：DPRAM读指针
charout：串行数据输出
bps_clk：位时钟（测试用）
SendFlag:发送标志（发送数据时为1）
开发环境：ISE8.4-verilog functions: DSP or microcontroller to the DPRAM of the FPGA to write a data (no more than 2K bytes, the first two bytes on behalf of the send data length), then gives the start signal send_start, this module automatically read the DPRAM data, set the baud rate specified in the DPRAM length of data sent. Interface signals Description: the send_start: Start FPGA serial send the pulse sys_rst: system reset pulse bps_setup: baud rate selection clk5_714: the 5.714MHz clock char_in: DPRAM read out on behalf of the sending data ReadPtr_w: the DPRAM Reading the pointer charout: serial data output bps_clk: SendFlag bit clock (test): Send logo (send data to 1)
Platform: |
Size: 1024 |
Author: 胡铁乔 |
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