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Description: DVB—S2中LDPC码编码器的FPGA设计与实现
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Size: 244894 |
Author: sss |
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Description: DVB—S2中LDPC码编码器的FPGA设计与实现-DVB-S2 in the LDPC code encoder FPGA Design and Implementation
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Size: 244736 |
Author: sss |
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Description: DVB系统的SDI数据数据传输接口，FPGA设计实现-DVB system SDI data transmission interface, FPGA Design and Implementation
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Size: 229376 |
Author: 梁光辉 |
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Description: DVB_T系统中信道编码的研究与FPGA实现，一篇很好的说是论文，caj阅读器浏览- Research and FPGA Implementation
of Channel Coding in DVB-T Systems
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Size: 1945600 |
Author: bai |
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Description: DVB_H信道编码调制的设计及其FPGA实现研究，供大家学习参考。-DVB_H channel coding modulation design and FPGA Realization for them to learn information.
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Size: 2475008 |
Author: 颜琳 |
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Description: DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
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Size: 708608 |
Author: 程钢 |
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Description:
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Size: 4829184 |
Author: 梅国强 |
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Description: Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于
数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍
了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its random and unexpected error has a strong error correction capabilities, widely used in digital video broadcasting (DVB) systems and other digital communications. Gives a GF (25) Domains RS (31, 23) algorithm of the encoder is introduced with a Field Programmable Gate Array (FPGA) RS encoder to achieve the principles and processes, and providing a circuit and simulation of the output waveform.
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Size: 360448 |
Author: 王彬 |
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