Search - floorplan

Search - floorplan - List

[TreeView] btree_win_v1.1_bin DL : 0: btree for floorplan using visual c++
Update : 2025-02-19 Size : 678kb Publisher : vimal
[Mathimatics-Numerical algorithms] floorplan-source-win32 DL : 0: test the resut l llke mjhue hbjhw -test the resut l llke mjhue hbjhw hhww
Update : 2025-02-19 Size : 14kb Publisher : amu
[Algorithm] GSA_FloorplanDesign DL : 0: This file contains a complete project on implementing mixed Genetic and Simulated Annealing alghorithms in try of solving Floorplan Design problems. In the code you can easily change some basic functions as population, temprature, it s changes. You can also try to change the ratio between genetic and anneling algorithms. The output of program gives you some basic comparision between GA and GSA algorithm ( time and best found solution)
Update : 2025-02-19 Size : 5mb Publisher : Antoni
[CAD] src DL : 0: 使用B*树以及模拟退火算法布置版图。有图形化界面。-Using B* tree and simulated annealing algorithm to generate IC floorplan. The software has a graphical interface.
Update : 2025-02-19 Size : 39kb Publisher : 杨毅
[OS program] floorplan DL : 0: the part of floorplan for design automation in the platform of matlab-the part of floorplan for design automation
Update : 2025-02-19 Size : 6kb Publisher : tong geng
[Other] Example-s3-1 DL : 0: 1.打开工程文件 2.打开LogicLock窗口，创建新区域 3.将data_buffer模块适配新建buffer_lock区域中 4.检查区域类型 5.关闭Optimize I/O选项 6.编译设计 7.反标注节点位置 8.观察Floorplan 输出LogicLock反标注信息-1. Open the project file 2. Open LogicLock window, create a new zone 3. The adapter module data_buffer New buffer_lock area 4. Check the zone type 5. Close the Optimize I/O options 6. Compile Design 7. Anti-marked node locations 8. Observe Floorplan Output LogicLock back annotation information
Update : 2025-02-19 Size : 2.44mb Publisher : zhuchaoyong
[Other] Files_Online2PDF DL : 0: physical design floorplan powerplan placement CTS Route
Update : 2025-02-19 Size : 2.42mb Publisher : praveenbw
[Education soft system] CAD algorithms for circuit layouts DL : 0: Source codes: src/cse788_layout.c - Code transform netlist output into magic file src/cse788_netlist.c - Implementation of optimzal netlist solver src/cse788_gordian.c - Implementation of gordian placement algorithm src/cse788_floorplan.c - Implementation of simulated annealing based floorplan algorithm. src/cse788_display.c - Graphic interface for the annealing and gordian. test/hw4.c - main function calling the modules src/plus/* - Helper functions used with the implementation. Binary: The executable for Windows is located in bin/debug/hw4.out, the dll's should be placed together with the executable. Usage: hw4.out Example: hw4.out "~((A*B)*C)" "layout.mag" ###Build: Environment: mingw/msys or any linux/unix distribution with GCC and GNU make. GSL1.1 (GNU Scientific Library) and SDL2 (Simple Direct media Layer) are required. Compilation: "make" in the project folder Run: "make run" to run with above example configuration.
Update : 2021-10-25 Size : 193.26kb Publisher : nalevihtkas