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Description: 目 錄 1
目 錄
Unix基本指令 第一章
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1.1 本章教學大綱...................................................1-2
1.2 Unix的歷史......................................................1-2
1.3 Unix基本指令簡介..........................................1-5
1.4 編輯器vi.........................................................1-45
1.5 Unix的基本檔案系統.....................................1-51
1.6 相關網站.........................................................1-60
1.7 課後習題相關網站.........................................1-61
CMOS VLSI設計概念與Design Flow 第二章
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2.1 本章教學大綱...................................................2-2
2.2 IC的各種設計方法..........................................2-2
2.3 MOS電晶體....................................................2-10
2.4 CMOS的技術.................................................2-16
2.5 Bottom Up與Top Down設計........................2-25
2.6 Full Custom IC的設計流程............................2-29
2.7 Design Frame work II之檔案結構..................2-33
2.8 CAD/CAE軟體的資料格式標準....................2-40
2.9 國科會晶片實現中心 ( CIC )........................2-42
2.10 作業.................................................................2-44
2 目 錄
第
如何進入Cadence 三章
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3.1 如何進入Cadence.............................................3-2
3.2 如何將Cadence 4.3.X的Lib轉成OPUS-97A 4.4版的Lib......................................................3-4
3.3 建立新的Library............................................3-12
3.4 建立新的cellview...........................................3-17
Schematic 第四章
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4.1 Schematic 指令介紹.......................................4-2
4.2 Schematic繪圖視窗選項介紹..........................4-3
4.3 實作範例：建立一Buffer的Schematic View4-27
4.4 將Schematic View轉出網路檔 (netlist) 的CDL out...................................................................4-30
Symbol 第五章
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5.1 Symbol View快速選擇介紹.............................5-2
5.2 Symbol繪圖視窗選擇項介紹...........................5-4
5.3 實作範例：建立一Buffer的Symbol View...5-22
Layout 第六章
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6.1 Layout View......................................................6-2
6.2 Layer Selection Window (LSW) 視窗..............6-3
6.3 Layout快速選項列介紹...................................6-3
6.4 Layout View繪圖視窗選擇項介紹..................6-6
6.5 實作範例：建立一Buffer的Layout View....6-37
目 錄 3
第
Dracula 七章
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7.1 Dracula介紹.....................................................7-2
7.2 DRC(Design Rule Checking).............................7-2
7.3 DRC錯誤範例說明........................................7-15
7.4 DRC Error Message.........................................7-24
7.5 ERC錯誤範例說明.........................................7-27
7.6 LVS(Layout vs. Schematic Check)..................7-32
7.7 LVS錯誤範例說明.........................................7-49
7.8 LVS的錯誤型態.............................................7-62
7.9 LPE(Layout Parameter Extraction)..................7-78
I/O Circuit及Package 第八章
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8.1 I/O Circuit概述.................................................8-2
8.2 基本分類...........................................................8-4
8.3 CIC之I/O PAD................................................8-9
8.4 I/O PAD的規劃..............................................8-28
8.5 範 例.............................................................8-34
8.6 包裝 (Package)...............................................8-36
SPICE Simulation 第九章
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9.1 本章教學大綱...................................................9-2
9.2 SPICE Simulation的基本概念..........................9-2
9.3 SPICE的語法...................................................9-5
9.4 用HSPICE來模擬............................................9-8
9.5 用PSPICE來模擬..........................................9-53
9.6 用IsSPICE來模擬..........................................9-58
9.7 用SBTSPICE來模擬.....................................9-68
4 目 錄
第
Design Guide 十章
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10.1 本章教學大綱.................................................10-2
10.2 Design for Reliability......................................10-2
10.3 Design for Testability....................................10-27
範例：JK FF 第十一章
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11.1 本章教學大綱.................................................11-2
11.2 JK正反器電路圖............................................11-2
11.3 建立所有的邏輯閘.........................................11-3
11.4 JK正反器之schematic及symbol view........11-10
11.5 用HSPICE來模擬JK正反器之狀態輸出...11-11
11.6 Debug............................................................11-16
11.7 PDRACULA的驗證.....................................11-29
教育性晶片製作申請程序及範例 附錄一
Design Rules實例 (Mead & Conway) 附錄二
XV使用說明 附錄三
將電路加入IOPAD的方法 附錄四
加入IOPAD的幾個動作 附錄五
積體電路電路布局保護法 附錄六
參考資料
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Size: 9318659 |
Author: g9676612@cycu.edu.tw |
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Description: by Randal L. Schwartz and Tom Phoenix
ISBN 0-596-00132-0
Third Edition, published July 2001.
(See the catalog page for this book.)
Learning Perl, 3rd Edition.
Table of Contents
Copyright Page
Preface
Chapter 1: Introduction
Chapter 2: Scalar Data
Chapter 3: Lists and Arrays
Chapter 4: Subroutines
Chapter 5: Hashes
Chapter 6: I/O Basics
Chapter 7: Concepts of Regular Expressions
Chapter 8: More About Regular Expressions
Chapter 9: Using Regular Expressions
Chapter 10: More Control Structures
Chapter 11: Filehandles and File Tests
Chapter 12: Directory Operations
Chapter 13: Manipulating Files and Directories
Chapter 14: Process Management
Chapter 15: Strings and Sorting
Chapter 16: Simple Databases
Chapter 17: Some Advanced Perl Techniques
Appendix A: Exercise Answers
Appendix B: Beyond the Llama
Index
Colophon -by Randal L. Schwartz and Tom Phoenix ISBN 0-596-00132-0 Third Edition, published July 2001. (See the catalog page for t his book.) Learning Perl, 3rd Edition. Table of Contents Page Copyright P reface Chapter 1 : Introduction Chapter 2 : Scalar Data Chapter 3 : Lists and Arrays Chapter 4 : Subroutines Chapter 5 : Hashes Chapter 6 : I/O Basics Chapter 7 : Concepts of Regular Expressions Chapter 8 : More About Regular Expressions Chapter 9 : Using Regular Expressions Chapter 10 : More Control Structures Chapter 11 : Filehandles and File Tests Chapter 12 : Directory Operations Chapter 13 : Manipulating Files and Directories Chapter 14 : Process Management Chapter 15 : Strings and Sorting Chapter 16 : Simple Databases Chapter 17 : Some Advanced Perl Techniques Appendix A : Exercise Answers
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Size: 1021952 |
Author: David Yin |
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Description: java信息系统设计原码: 书籍借阅管理系统\产品管理系统\ 学生管理系统\房产管理系统-java source of information system design: books to borrow Management System Product Management System Student Management System Property Management System
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Size: 363520 |
Author: 李想 |
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Description: 热血江湖原代码-rxuejdjddssfdsfsdfdsdsfdf
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Size: 364544 |
Author: 1363443 |
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Description: ligne de partage des eaux sur matlab
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Size: 2048 |
Author: sofie |
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Description: image processing, ligne de partage des eaux
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Size: 267264 |
Author: youssef |
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Description: La LPE est un algorithme en traitement de l image qui permet de segmenter
l image en région homogène. C est une technique très puissante simulant
l immersion d un relief topologique par les eaux.
L algorithme implémenté est une réponse au principe de S.Beucher: LPE sans
biais et avec marqueur.
L immersion commence par les marqueurs et à chaque fois que deux bassins
versant se rencontre, une "digue" est irriguée séparant les deux bassins.
L ensemble des digues correspond à la ligne de partage des eaux.
Les marqueurs permettent de contrô ler la segmentation puisqu il y aura autant
de région que de marqueur.
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Size: 224256 |
Author: abdelghni |
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Description: Watershed transform segmentation des images avec ligndes de patrage des eaux over segmentation LPE
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Size: 1024 |
Author: irina |
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Description: 导出立方非线性器的复低通等效模型,对带通模型和LPE模型进行仿真-Export control of complex cubic nonlinear low-pass equivalent model of band-pass simulation model and the LPE model
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Size: 71680 |
Author: Delia |
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Description: An image segmentation algorithm for LPE image segmentation
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Size: 1024 |
Author: Carole |
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Description: 集成电路的后端设计包括版图设计和验证。采用Cadence的Virtuoso Layout Editor的版图设计环境进行版图设计。利用Virtuoso Layout Editer的集成验证工具DIVA进行了验证。验证的整个的过程包括：设计规则检查（Design Rule Checking 简称DRC ）、电学规则检查（Electronics Rule Checking 简称ERC）、电路图版图对照（Layout Versus Schematic 简称LVS）、以及版图寄生参数提取（Layout Parameter Extraction 简称LPE）-The integrated circuit the backend design including layout design and verification. Layout using Cadence Virtuoso Layout Editor environment for layout design. Integrated verification tools using Virtuoso Layout Editer DIVA verified. Verification of the entire process, including: design rule checking (Design Rule Checking DRC), electrical rule checking (Electronics Rule Checking ERC) Schematic layout control (Layout Versus Schematic LVS), and the layout parasitic extraction (Layout Parameter Extraction referred LPE)
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Size: 149504 |
Author: alan |
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Description: sst_pci.c - SST (LPE) driver init file for pci enumeration.
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Size: 2048 |
Author: zasenghj |
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Description: sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
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Size: 5120 |
Author: puidenbl |
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