Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - right shifter

Search list

[VHDL-FPGA-Verilog] EX

Description: Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
Platform: | Size: 4096 | Author: hugo | Hits:

[VHDL-FPGA-Verilog] 1_LAB

Description: Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
Platform: | Size: 6119424 | Author: hugo | Hits:

[VHDL-FPGA-Verilog] zj

Description: vhdl编程 实现移位寄存器 左移动和右移动-VHDL Programming shifter left and right moving mobile
Platform: | Size: 1024 | Author: wangjun | Hits:

[VHDL-FPGA-Verilog] barrel_shifter

Description: VHDL实现的桶型移位器，能在一个时钟周期实现对数据的（0－12位）算术右移-VHDL implementation of a barrel—shifter, able to achieve at one clock cycle of data (0-12 bit) Arithmetic Shift Right
Platform: | Size: 1024 | Author: 过时无双 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Platform: | Size: 129024 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] rshift1

Description: right shifter using vhdl,
Platform: | Size: 1024 | Author: hatela | Hits:

[VHDL-FPGA-Verilog] shifter

Description: vhdl,双向移位寄存器，实现置数，左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation
Platform: | Size: 32768 | Author: 王晓虎 | Hits:

[VHDL-FPGA-Verilog] jincunqi

Description: VHDL语言实现的移位器，功能包括算术左移和右移，逻辑左移和右移，循环左移和右移。-VHDL language implementation of the shifter, left and right shift functions include arithmetic, logical left and shifted to the right, left and right shift cycle.
Platform: | Size: 285696 | Author: 吴越 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 8位移位器，实现算术左、右移位，逻辑左右移位和循环左右移位。-8-bit shift device to achieve arithmetic left and right shift, logical shift left shift and cycle around.
Platform: | Size: 215040 | Author: 龙一 | Hits:

[Software Engineering] Long_shift_gate_level

Description: 1. Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design. 9. The logarithmic shifter is based on a staged approach (powers of 2). A simple architecture is described as Figure 1.
Platform: | Size: 6144 | Author: chen-che,wemg | Hits:

[VHDL-FPGA-Verilog] e4

Description: 用VHDL实现左右移位寄存器，代码简单，易于实现-left-right shifter
Platform: | Size: 4096 | Author: 蚂蚁 | Hits:

[DSP program] barrel_shifter

Description: A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance. For example, take a four-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA in this case, no bits are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including being a useful component in microprocessors (alongside the ALU)-A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance. For example, take a four-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA in this case, no bits are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including being a useful component in microprocessors (alongside the ALU)
Platform: | Size: 99328 | Author: Leyla | Hits:

[VHDL-FPGA-Verilog] barrelshifter32

Description: 32位桶形移位器，可以实现算数右移、逻辑右移、算术左移和逻辑左移。-32-bit barrel shifter, can achieve an arithmetic right shift, logical shift right, left arithmetic and logical left.
Platform: | Size: 1024 | Author: ellen | Hits:

CodeBus www.codebus.net