Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed. Platform: |
Size: 179551 |
Author:李中伟 |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed. Platform: |
Size: 179200 |
Author:李中伟 |
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Description: 针对超声波应用系统易受噪声干扰以及超声波信号的空间衰减现象影响, 从而要求
超声波传感器工作在其最佳特性的特点, 论证了驱动脉冲信号的控制精度对传感器工作特
性的影响, 给出了传感器驱动信号脉冲宽度与传感器频率之间的最佳关系式, 提出了采用复
杂可编程逻辑器件(CPLD) 产生传感器驱动控制信号的方法, 将该方法应用于一超声波流
量计测量系统中, 得到了比传统型单片机控制电路更好的控制精度和控制效果。-For ultrasonic applications vulnerable to noise interference and attenuation of ultrasonic signals in the effects of space and thus require ultrasonic sensors work best features in its characteristics, demonstrated that the drive pulse signal of the control accuracy of the sensor characteristics of the work, given the sensor-driven signal pulse width and frequency sensors of the best relationship between the proposed use of complex programmable logic device (CPLD) have a sensor-driven control signal approach, the method is applied to one ultrasonic flowmeter measurement system has been more than traditional single-chip control circuit better control precision and control. Platform: |
Size: 223232 |
Author:李明 |
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Description: 本系统采用调频方式实现了主站至从站的单工语音及数据传输业务。发射机以单片机SPCE061A为核心，采用MC145151锁相环完成FM调制等功能；接收机采用CXA1691完成FM解调功能；引入双音频编解码完成数据传输；利用市售红外遥控器实现了发射机英文字符的输入。-The system uses a frequency modulation approach to achieve the main points of the simplex from the station voice and data transmission. SPCE061A transmitter for a single-chip core, the MC145151 PLL FM modulation functions achieve receiver using FM demodulation functions achieve CXA1691 the introduction of dual-audio codec achieve data transmission the use of infrared remote control market implementation of the launching machine input English characters. Platform: |
Size: 74752 |
Author:兴中 |
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Description: 研究了基于滤波器组的单载波频域均衡技术的基本原理和实现方法,通过系统对比基于滤波器组的方法与基于FFT方法的异同之处,从其产生的机理上阐明了基于滤波器组的单载波频域均衡技术能够克服FFT 方式的主要缺点的原因-Of filter-based single-carrier frequency domain equalization technology, the basic principle and method, through the system, filter-based approach compared with the FFT method based on the similarities and differences between, from production to clarify the mechanism of the filter-based single-carrier frequency domain equalization techniques to overcome the main drawback of FFT method because Platform: |
Size: 265216 |
Author:姜烨 |
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Description: 频率的测量实际上就是在1s时间内对信号进行计数，计数值就是信号频率。用单片机设计频率计通常采用两种办法，第一种方法是使用单片机自带的计数器对输入脉冲进行计数；第二种方法是单片机外部使用计数器对脉冲信号进行计数，计数值再由单片机读取。-In the measurement of frequency is actually 1s to count time signal, numerical is signal frequency. Using single-chip microcomputer frequency plan by using two kinds of method, usually the first approach is to use own counter chip counting input pulses, The second method is to use external counter pulse signal count by MCU, numerical read again. Platform: |
Size: 17408 |
Author:倪萍波 |
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Description: In the measurement of frequency is actually 1s to count time signal, numerical is signal frequency. Using single-chip microcomputer frequency plan by using two kinds of method, usually the first approach is to use own counter chip counting input pulses, The second method is to use external counter pulse signal count by MCU, numerical read again. Platform: |
Size: 17408 |
Author:倪萍波 |
Hits:
Description: A Software-Defi ned GPS and Galileo Receiver
A Single-Frequency Approach这本书的源代码-A Software-Defined GPS and Galileo Receiver A Single-Frequency Approach this book' s source code Platform: |
Size: 506880 |
Author:chennaruto |
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Description: Multiple input multiple output techniques combined
with orthogonal frequency division multiplexing (MIMO-OFDM)
provide a promising approach for wireless systems. However, a
serious drawback of the OFDM system is the high peak-toaverage
power ratio (PAPR), which may severely affect the
power efficiency of RF power amplifiers. In this paper, we
propose a simple method to reduce the PAPR of MIMO-OFDM
signals based on the use of unused subcarriers. Instead of
processing the signals at each transmitter separately, a peak
cancelling signal is generated at one antenna and is then applied
to all the others with only simple modifications. Simulation has
shown that a minimum 2 dB reduction in PAPR can be achieved
for all transmit signals using this approach. As the signal
processing is nearly all done at a single transmitter, repetition of
the operations at each transmitter is avoided, and therefore the
overall cost of the system can be significantly reduced. Platform: |
Size: 714752 |
Author:payal |
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Description: Multiple input multiple output techniques combined
with orthogonal frequency division multiplexing (MIMO-OFDM)
provide a promising approach for wireless systems. However, a
serious drawback of the OFDM system is the high peak-toaverage
power ratio (PAPR), which may severely affect the
power efficiency of RF power amplifiers. In this paper, we
propose a simple method to reduce the PAPR of MIMO-OFDM
signals based on the use of unused subcarriers. Instead of
processing the signals at each transmitter separately, a peak
cancelling signal is generated at one antenna and is then applied
to all the others with only simple modifications. Simulation has
shown that a minimum 2 dB reduction in PAPR can be achieved
for all transmit signals using this approach. As the signal
processing is nearly all done at a single transmitter, repetition of
the operations at each transmitter is avoided, and therefore the
overall cost of the system can be significantly reduced. Platform: |
Size: 5120 |
Author:payal |
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Description: 基于FPGA的单精度浮点数乘法器设计，本文设计了一个基于FPGA的单精度浮点数乘法器。乘法器为五级流水线结构。设计中采用了改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构，减少了部分积的数目，缩短了部分积累加的耗时；提出了对尾数定点乘法运算中Wallace树产生的2个伪和采用部分相加的处理方式，有效地提高了的运算速度；并且加入了对特殊值的处理模块，完善了乘法器的功能。单精度浮点数乘法器在Altera DE2开发板上进行了验证，其在Cyclone II EP2C35F672C6器件上的最高工作频率达到212.13 MHz。-FPGA-based single-precision floating-point multiplier design, design of an FPGA-based single-precision floating-point multiplier. Multipliers for the five pipeline structure. Design with improved offset the redundancy Booth3 algorithm and leapfrog Wallace tree structure to reduce the number of partial product, shorten the time-consuming part of the accumulated added on the Wallace tree in the fixed-point multiplication of mantissa two false and part of the additive approach, effectively improving the processing speed and joined the special value of the processing module, and improve the function of the multiplier. Single-precision floating-point multiplier on Altera DE2 development board for verification, its maximum operating frequency of the Cyclone II EP2C35F672C6 device to 212.13 MHz. Platform: |
Size: 600064 |
Author:kudding |
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Description: We demonstrate a new approach to CARS spectroscopy by effi ciently syn- thesizing synchronized narrow-bandwidth (less than 10 cm− 1) pump and Stokes pulses (frequency diff erence continuously tunable upto ～3000 cm− 1) based on spectral compres- sion together with second harmonic generation (in periodically-poled nonlinear crystals) of femtosecond pulses emitted by a single compact Er-fi bre oscillator. For a far better signal to non-resonant background contrast, interferometric CARS (I-CARS) is demonstrated and CARS signal enhancement upto three orders of magnitude is achieved by construc- tive interference with an auxiliary local oscillator at anti-Stokes fi eld, also synthesized by spectral compression of pulses emitted the same fi bre oscillator.
-We demonstrate a new approach to CARS spectroscopy by effi ciently syn- thesizing synchronized narrow-bandwidth (less than 10 cm− 1) pump and Stokes pulses (frequency diff erence continuously tunable upto ～3000 cm− 1) based on spectral compres- sion together with second harmonic generation (in periodically-poled nonlinear crystals) of femtosecond pulses emitted by a single compact Er-fi bre oscillator. For a far better signal to non-resonant background contrast, interferometric CARS (I-CARS) is demonstrated and CARS signal enhancement upto three orders of magnitude is achieved by construc- tive interference with an auxiliary local oscillator at anti-Stokes fi eld, also synthesized by spectral compression of pulses emitted the same fi bre oscillator.
Platform: |
Size: 1604608 |
Author:ajay |
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Description: 本文提出了一种新的识别方法通过建立一个联合
delay-cyclic频率特性决定功能,利用二阶循环的不同特点
累积量的正交频分复用(OFDM)信号和单载波线性数字调制
(SCLD)信号,延时域和循环频率域。-This paper presents a new recognition approach through establishing a joint
delay-cyclic frequency feature decision function, which exploits the different features of the second-order cyclic
cumulants for orthogonal frequency division multiplexing (OFDM) signals and single carrier linear digitally modulated
(SCLD) signals, in both time delay domain and cyclic frequency domain. Platform: |
Size: 497664 |
Author:徐叉叉 |
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Description: 对于系统单参数分岔图的计算共有以下的几种方法：
1）最大值法
即对系统微分方程（组）进行求解，对求解的结果用getmax函数进行取点，并绘图。
2）Poincare截面法
对系统参数的每一次取值，绘制其Poincare截面，进而得到其分岔图。
这种方法需要注意的是，自治系统的Poincare截面是选取一超平面，平面上点的分布即构成一Poincare截面，非自治系统的Poincare截面则是根据系统激励的频率进行取点并绘图。(There are several methods for calculating the single parameter bifurcation diagram of the system.
1) maximum value method
That is, the solution of the system differential equation (Group) is carried out, and the results of the solution are taken with the getmax function, and the drawing is drawn.
2) Poincare cross section method
For each value of the system parameters, the Poincare section of the system is drawn, and then the bifurcation diagram is obtained.
Need to pay attention to this approach is that the Poincare section is selected a plane autonomous system, the point of the plane distribution is composed of Poincare section, Poincare section of non autonomous systems is the access point and drawing according to the system excitation frequency.) Platform: |
Size: 4741120 |
Author:Andyni123 |
Hits:
Description: (Applied and Numerical Harmonic Analysis) Kai Borre, Dennis M. Akos, Nicolaj Bertelsen, Peter Rinder, Søren Holdt Jensen - A Software-Defined GPS and Galileo Receiver_ A Single-Frequency Approach (App Platform: |
Size: 1932550 |
Author:ybouhafsi31@gmail.com |
Hits:
Search - single frequency approach