[VHDL-FPGA-Verilog] 4对1复用器

Description: 设计一个4对1复用器（输入：I3 I2 I1 I0，输出：F ，另有两个输入控制端S1与S0控制输出选择），真值表如图1。 S1 S0 F 0 0 0 1 1 0 1 1 I0 I1 I2 I3
Platform: | Size: 4239501 | Author: 3534800699@qq.com | Hits:

[Open-source hardware] shifting registers

Description: this recource will shift register
Platform: | Size: 58216 | Author: osama936611914 | Hits:

[VHDL-FPGA-Verilog] MPX CPU

Description: Open source implementation of MPX CPU (mips compatible) in Verilog
Platform: | Size: 14723 | Author: xptogudovan | Hits:

[VHDL-FPGA-Verilog] S1 CPU core

Description: S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the l
Platform: | Size: 1114206 | Author: xptogudovan | Hits:

[VHDL-FPGA-Verilog] Flexpret CPU core

Description: Flexpret is RISCv implementation core hardware multithreaded
Platform: | Size: 1785155 | Author: xptogudovan | Hits:

[SCM] AC696N SDK

Description: AC696N SDK for USB Bluetooth Hardware very usefull
Platform: | Size: 81737570 | Author: androsakthi@gmail.com | Hits:

[SCM] SMEC90ST SDK

Description: SMEC90ST SDK for Encryption Chip for prevent copy in your code very small package SOT23-5
Platform: | Size: 2164195 | Author: androsakthi@gmail.com | Hits:

[SCM] AC695N-SDK

Description: AC695N SDK for Bluetooth ear phone software
Platform: | Size: 26715433 | Author: androsakthi@gmail.com | Hits:

[hardware design] 兆易ARM固件开发库

Description: GD32, 固件,C语言,国产化;兆易半导体Cortex-F4系列ARM芯片开发库
Platform: | Size: 3967871 | Author: ciomplxl@163.com | Hits:

[SCM] adxl345加速度传感器历程

Description: 基于stc89c51的简单的adxl345加速度传感器历程 具体需自行改动
Platform: | Size: 56328 | Author: VioletTZ | Hits:

[Other Embeded program] tiny project

Description: experiment attiny 85 embedded
Platform: | Size: 918 | Author: kaeyxetaners | Hits:

[Embeded Linux] rt1295 openwrt

Description: openwrt porting for rt1295.
Platform: | Size: 36439687 | Author: pixychu@hotmail.com | Hits: