TAXI_fee_counter in EDA platform with a single CPL - CodeBus

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Title: TAXI_fee_counter

Category:
VHDL-FPGA-Verilog
Tags:
[Text]
File Size:
2.44kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
laiweidong1979

Description: in EDA platform with a single CPLD constitute the digital system design and implementation process.

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