Description: Commonly used in FPGA development serial module, after I debug, very useful
- [UART] - Their use VHDL to write a serial program
- [uart_rx] - actel A3P250 fpga with VERILOG HDL Seria
- [uart] - VHDL prepared the design of serial async
- [cyclic] - FPGA serial communication program, accep
- [uart_receiver] - Very good info. for RS-232 receive VHDL
- [Uart] - Using FPGA, VHDL realize the UART core,
- [UART_rec] - Verilog serial receive process, ACTEL Fu
- [qts_qii53009] - Quartus II SignalTap II documentation, d
- [fifo] - Synchronizing FIFO creates a 256x8 synch
- [fpga-dm9000a] - A project engineering, hardware contains
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