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Title:
phase_detector_top_v1.1
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
224.84kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
zhanaotongxue
Description:
Virlog languages use a phase-locked loop procedure. Can be directly applied in the CPLD.
Downloaders recently:
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