ad_convert The CPLD control time sequence is trans - CodeBus

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

FAQ Fav

Location:

Title: ad_convert

Category:
VHDL-FPGA-Verilog
Tags:
[Text]
File Size:
198.9kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
nannan_ti

Description: The CPLD control time sequence is transmitted via usb to the PC's VHDL source code for an ecg machine.

Downloaders recently: [More information of uploader nannan_ti]

To Search: USB

[usbschdoc] - usb chip design schematics, contains USB
[usb data transfer] - code for data transfer through usb, can
[LA_USB] - between USB and CPLD transmission, has c
[pingpongjiegou] - VHDL compiler, the procedure is GPIF USB
[altera_USB_blaste] - altera USB blaste produced full set of i
[USB2_0CY7C68013FPGAVerilogHD] - cy68013 interface with the FPGA design v
[DE2_USB_API] - Altera de2 development board to provide
[545465C6546] - Using C to write the word games is a lot
[spring] - Chinese spring2.0 reference manual, very
[USBcomm] - fpga usb interface system design example

File list (Check if you may need any files):

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

1999-2018 CodeBus All Rights Reserved.