Description: FPGA development of Verilog HDL entry procedures- water lights, the real available, authentication is passed, the project environment for Altera Quartus
- [cpld_bus] - CPLD bus Verilog HDL code, the PLD-10 Qu
- [modlesimasimpletutorial.Rar] - a good Chinese language teaching system,
- [waterlight] - simple experiment water lights, four lig
- [89_full_adder] - full adder design code, verilog language
- [sin] - Quartus II design sinusoidal signal gene
- [fpga] - Functions/Classes:
- [dds] - Direct frequency synthesizer using veril
- [Matlabxdjm] - This is the MATLAB modeling channel to t
- [HwLog10] - It is a verilog design of LOG10 calculat
- [123] - Quartus-based, the state machine to achi
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