Description: In addition to the completion of the use of a chip clock source, buttons, speakers and monitors (digital tube) all the figures outside the circuit functions. All digital logic functions are used in the CPLD devices VHDL language. This design has a small size, short design cycle (the design process to achieve timing simulation), debugging convenient, low failure rate, modify the characteristics of easy upgrade
To Search:
File list (Check if you may need any files):
CPLDVHDL2.doc
Download