Description: The use of embedded digital clock nios2 the design and realization of the first to use quartus2 in sopc builder design CPU core, and then nios2 Zhongyong C language to realize the function of digital clock
File list (Check if you may need any files):
nios_II_lab
...........\altera_vhdl_support.vhd
...........\avalon_pwm.v
...........\avalon_pwm.vhd
...........\cmp_state.ini
...........\connector_pll.bsf
...........\connector_pll.v
...........\crc.bdf
...........\crc_mux.bdf
...........\crc_peripheral.v
...........\crc_peripheral.vhd
...........\custominstruction_cpu.vhd
...........\db
...........\..\niosII_lab.db_info
...........\..\niosII_lab.eco.cdb
...........\..\niosII_lab.sld_design_entry.sci
...........\delay_reset_block.bdf
...........\delay_reset_block.bsf
...........\endian_convert.bdf
...........\high_res_timer.vhd
...........\ic_tag_ram.mif
...........\niosII_generation_script
...........\niosII_lab.bdf
...........\niosII_lab.qpf
...........\niosII_lab.qsf
...........\niosII_lab.qws
...........\niosII_lab_assignment_defaults.qdf
...........\niosII_log.txt
...........\niosII_setup_quartus_native_synthesis.tcl
...........\reg16.bdf
...........\reset_counter.v
...........\rf_ram_a.mif
...........\rf_ram_b.mif
...........\Setup_Cyclone_1C20.tcl
...........\Setup_StratixII_2S60.tcl
...........\Setup_Stratix_1S10.tcl
...........\Setup_Stratix_1S10_ES.tcl
...........\Setup_Stratix_1S40.tcl
...........\seven_seg_pio.vhd
...........\software
...........\........\altera_avalon_pwm.h
...........\........\crc.c
...........\........\crcci.c
...........\........\crcdma.c
...........\........\pwm.c
...........\........\simple.c
...........\sopc_builder_debug_log.txt
...........\sysid.vhd
...........\sys_clk_timer.vhd
...........\xor_shift_crc16_ccitt.bdf
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