Description: A VGA display program design, in this example VGA Interface VGA can display 512 kinds of different colors. This design applies to EFX-SP3200S EFX-SP3400S
To Search:
- [DE2_SD_Card_Audio] - SD card reader audio data from the VGA d
- [VGA] - FPGA-driven interface VGA display charac
- [oc_i2c_master] - This is an I2C of IP. Kaodao altera dire
- [xitong1] - A FPGA-based implementation for the full
- [FPGA_VHDL_code] - FPGA to learn very valuable information,
File list (Check if you may need any files):
pro102
......\bit
......\...\rhic_vga_top_sp3200s.bit
......\constrain
......\.........\vga_top_v3.ucf
......\ise_pro
......\.......\ise81_verilog
......\.......\.............\ise81_verilog.ise
......\.......\.............\ise81_verilog.ise_ISE_Backup
......\.......\.............\rhic_vga_top.bgn
......\.......\.............\rhic_vga_top.bld
......\.......\.............\rhic_vga_top.cmd_log
......\.......\.............\rhic_vga_top.drc
......\.......\.............\rhic_vga_top.lso
......\.......\.............\rhic_vga_top.ncd
......\.......\.............\rhic_vga_top.ngc
......\.......\.............\rhic_vga_top.ngd
......\.......\.............\rhic_vga_top.ngr
......\.......\.............\rhic_vga_top.pad
......\.......\.............\rhic_vga_top.par
......\.......\.............\rhic_vga_top.pcf
......\.......\.............\rhic_vga_top.prj
......\.......\.............\rhic_vga_top.stx
......\.......\.............\rhic_vga_top.syr
......\.......\.............\rhic_vga_top.twr
......\.......\.............\rhic_vga_top.twx
......\.......\.............\rhic_vga_top.unroutes
......\.......\.............\rhic_vga_top.ut
......\.......\.............\rhic_vga_top.xpi
......\.......\.............\rhic_vga_top.xst
......\.......\.............\rhic_vga_top_map.mrp
......\.......\.............\rhic_vga_top_map.ncd
......\.......\.............\rhic_vga_top_map.ngm
......\.......\.............\rhic_vga_top_pad.csv
......\.......\.............\rhic_vga_top_pad.txt
......\.......\.............\rhic_vga_top_summary.html
......\.......\.............\rhic_vga_top_vhdl.prj
......\.......\.............\xst
......\.......\.............\...\dump.xst
......\.......\.............\...\........\rhic_vga_top.prj
......\.......\.............\...\........\................\ngx
......\.......\.............\...\........\................\...\notopt
......\.......\.............\...\........\................\...\opt
......\.......\.............\...\projnav.tmp
......\.......\.............\...\work
......\.......\.............\...\....\hdllib.ref
......\.......\.............\...\....\vlg17
......\.......\.............\...\....\.....\sync__gen__50m.bin
......\.......\.............\...\....\vlg20
......\.......\.............\...\....\.....\char__rom__rhic.bin
......\.......\.............\...\....\vlg51
......\.......\.............\...\....\.....\rhic__vga__top.bin
......\.......\.............\_impact.cmd
......\.......\.............\_impact.log
......\.......\.............\_ngo
......\.......\.............\....\netlist.lst
......\.......\.............\_xmsgs
......\.......\.............\......\bitgen.xmsgs
......\.......\.............\......\map.xmsgs
......\.......\.............\......\ngdbuild.xmsgs
......\.......\.............\......\par.xmsgs
......\.......\.............\......\trce.xmsgs
......\.......\.............\......\xst.xmsgs
......\readme.txt
......\rtl
......\...\verilog
......\...\.......\char_rom_rhic.V
......\...\.......\rhic_vga_top.v
......\...\.......\sync_gen_50m.v
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