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Title: modelsim Download
 Description: SOPC Builder to create the CPU, to meet the simple VHDL software simulation
 Downloaders recently: [More information of uploader happyrogerli]
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modelsim
........\Add2In.vhd
........\Add2In_tb.vhd
........\Add_full_0_delay.v
........\Add_half_0_delay.v
........\AOI_5_CA0.v
........\AOI_5_CA3.v
........\DivClk.cr.mti
........\DivClk.mpf
........\DivClk.vhd
........\DivClk2HDL.vhd
........\DivClk2Proj.cr.mti
........\DivClk2Proj.mpf
........\latch_rp.v
........\new.v
........\Result.dat
........\shiftreg.v
........\TestBench
........\testbench1.v
........\TestBenchnew
........\TestBenchTest.cr.mti
........\TestBenchTest.mpf
........\TestData.dat
........\t_Add_half.v
........\vsim.wlf
........\vsim_stacktrace.vstf
........\wave1.do
........\wlft7m4jgn
........\wlftb3c7rj
........\wlftbjs6kx
........\work
........\....\@a@o@i_5_@c@a0
........\....\..............\_primary.dat
........\....\..............\_primary.vhd
........\....\@add_half_0_delay
........\....\.................\verilog.asm
........\....\.................\_primary.dat
........\....\.................\_primary.vhd
........\....\add2in
........\....\......\behavior.dat
........\....\......\_primary.dat
........\....\divclk
........\....\......\behavioral.dat
........\....\......\_primary.dat
........\....\divclk1
........\....\.......\behavioral.dat
........\....\.......\_primary.dat
........\....\divclk1_tb
........\....\..........\behavior.dat
........\....\..........\_primary.dat
........\....\latch_rp
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\shift_reg
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\tb
........\....\..\a_tb.dat
........\....\..\_primary.dat
........\....\testbench
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\t_@add_half
........\....\...........\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\_info
........\....\_opt
........\....\....\work_tb_a_tb.asm
........\....\....\work__info
........\....\....\_deps
........\....\....\__model_tech_.._ieee__info
........\....\....\__model_tech_.._std__info
........\....\_opt1
........\....\.....\work_divclk1_behavioral.asm
........\....\.....\work__info
........\....\.....\_deps
........\....\.....\__model_tech_.._ieee__info
........\....\.....\__model_tech_.._std__info
........\....\_opt2
........\....\.....\work_divclk1_behavioral.asm
........\....\.....\work_divclk1_tb_behavior.asm
........\....\.....\work__info
........\....\.....\_deps
........\....\.....\__model_tech_.._ieee__info
........\....\.....\__model_tech_.._std__info
........\....\_temp
........\xuexi.cr.mti
........\xuexi.mpf
    

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