Description: Three of the voting procedure, with VerilogHDL Writing, and I hope to help everyone
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vote_1
......\db
......\..\prev_cmp_vote_1.map.qmsg
......\..\prev_cmp_vote_1.qmsg
......\..\vote_1.analyze_file.qmsg
......\..\vote_1.cbx.xml
......\..\vote_1.cmp.rdb
......\..\vote_1.db_info
......\..\vote_1.eco.cdb
......\..\vote_1.map.qmsg
......\..\vote_1.sld_design_entry.sci
......\..\vote_1.tis_db_list.ddb
......\vote_1.flow.rpt
......\vote_1.map.rpt
......\vote_1.map.summary
......\vote_1.qpf
......\vote_1.qsf
......\vote_1.qws
......\vote_1.v
......\vote_1.v.bak
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