Description: The number of locks: S0 is the reset state: password is 00000001, Guan Suo. S1 is the unlock state. Password to modify the state of S2: the code will enter a new password lock clearance. Hardware used to achieve FPGA2000
To Search:
- [elock] - Electronic code lock, enter the three er
- [suo] - 4 binary code lock, someone else may hav
- [08080212109337] - Unlock the completion of overtime alarm,
- [vhdl4] - The number of locks: 1. System has prese
- [experiment_7] - ROM-based sine wave generator of the des
- [TelikiErgasiaMaroulis] - an example of linked list for storage of
- [e3] - CNTR 4: will be conducted at 50MHz clock
- [VHDL-topics-Electronic-locks] - VHDL design of the password lock feature
File list (Check if you may need any files):
experiment_8
............\cmp_state.ini
............\db
............\..\lcok.db_info
............\..\lcok.eco.cdb
............\..\lcok.sld_design_entry.sci
............\..\lcok_cmp.qrpt
............\..\lock.smp_dump.txt
............\lcok.asm.rpt
............\lcok.cdf
............\lcok.done
............\lcok.fit.eqn
............\lcok.fit.rpt
............\lcok.fit.summary
............\lcok.flow.rpt
............\lcok.map.eqn
............\lcok.map.rpt
............\lcok.map.summary
............\lcok.pin
............\lcok.pof
............\lcok.qsf
............\lcok.sof
............\lcok.tan.rpt
............\lcok.tan.summary
............\lcok.vhd
............\lcok_description.txt
............\lock.qpf
............\lock.qws
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