- Category:
- MiddleWare
- Tags:
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- File Size:
- 2.7kb
- Update:
- 2008-10-13
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- Uploaded by:
- qiangbing02
Description: CPLD-based counters realize optical ranging, single-chip microcomputer that contains timing control and realize the adoption of Verilog simulation
- [countqi] - Asynchrony preset counter reset the Veri
- [MCU-counter] - MCU with verilog counter with MCU counte
- [ro_cnt] - Small counter coding, the use of Verilog
- [22345] - C
- [config_dac] - Verilog realize spi interface FPGA to ac
- [C1.0] - C Language Learning knowledge and help C
- [uart] - FPGA serial modules, FPGA implementation
- [13898394fiber-laser] - Fiber laser simulation of reference, a r
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