2选1
....\db
....\..\Vhdl1.asm.qmsg
....\..\Vhdl1.cbx.xml
....\..\Vhdl1.cmp.cdb
....\..\Vhdl1.cmp.hdb
....\..\Vhdl1.cmp.kpt
....\..\Vhdl1.cmp.logdb
....\..\Vhdl1.cmp.rdb
....\..\Vhdl1.cmp.tdb
....\..\Vhdl1.cmp0.ddb
....\..\Vhdl1.dbp
....\..\Vhdl1.db_info
....\..\Vhdl1.eco.cdb
....\..\Vhdl1.eds_overflow
....\..\Vhdl1.fit.qmsg
....\..\Vhdl1.hier_info
....\..\Vhdl1.hif
....\..\Vhdl1.map.cdb
....\..\Vhdl1.map.hdb
....\..\Vhdl1.map.logdb
....\..\Vhdl1.map.qmsg
....\..\Vhdl1.pre_map.cdb
....\..\Vhdl1.pre_map.hdb
....\..\Vhdl1.psp
....\..\Vhdl1.rtlv.hdb
....\..\Vhdl1.rtlv_sg.cdb
....\..\Vhdl1.rtlv_sg_swap.cdb
....\..\Vhdl1.sgdiff.cdb
....\..\Vhdl1.sgdiff.hdb
....\..\Vhdl1.signalprobe.cdb
....\..\Vhdl1.sim.hdb
....\..\Vhdl1.sim.qmsg
....\..\Vhdl1.sim.rdb
....\..\Vhdl1.sim.vwf
....\..\Vhdl1.sld_design_entry.sci
....\..\Vhdl1.sld_design_entry_dsc.sci
....\..\Vhdl1.syn_hier_info
....\..\Vhdl1.tan.qmsg
....\..\wed.zsf
....\Vhdl1.asm.rpt
....\Vhdl1.done
....\Vhdl1.fit.rpt
....\Vhdl1.fit.smsg
....\Vhdl1.fit.summary
....\Vhdl1.flow.rpt
....\Vhdl1.map.rpt
....\Vhdl1.map.summary
....\Vhdl1.pin
....\Vhdl1.qpf
....\Vhdl1.qsf
....\Vhdl1.qws
....\Vhdl1.sim.rpt
....\Vhdl1.tan.rpt
....\Vhdl1.tan.summary
....\vhdl1.txt
....\Vhdl1.vhd
....\Vhdl1.vwf