Description: Fifo generic design, with a testbench, and design_flow
To Search:
- [FIFO] - Asynchronous FIFO controller Verilog Des
- [afifo] - Asynchronous fifo of Verilog procedures,
- [fifov1] - FIFO (FIFO queue) is usually used for da
- [FIFO] - Asynchronous FIFO verilog realize realiz
- [PLL] - PLL clock module Quartus II platform att
- [FIFO] - Universal Asynchronous FIFO Verilog desi
- [ddr_dimm] - 256Mb_ddr achieve ddr_dimm operation
- [DDK_for_tidsp] - tidsp the ddk, writing dsp driver help
- [PLL] - verilog PLL code, and the function of PL
File list (Check if you may need any files):
generic_fifos
.............\bench
.............\.....\CVS
.............\.....\...\Entries
.............\.....\...\Repository
.............\.....\...\Root
.............\.....\verilog
.............\.....\.......\CVS
.............\.....\.......\...\Entries
.............\.....\.......\...\Repository
.............\.....\.......\...\Root
.............\.....\.......\test_bench_top.v
.............\CVS
.............\...\Entries
.............\...\Repository
.............\...\Root
.............\doc
.............\...\CVS
.............\...\...\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\README.txt
.............\rtl
.............\...\CVS
.............\...\...\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\verilog
.............\...\.......\CVS
.............\...\.......\...\Entries
.............\...\.......\...\Repository
.............\...\.......\...\Root
.............\...\.......\generic_fifo_dc.v
.............\...\.......\generic_fifo_dc_gray.v
.............\...\.......\generic_fifo_lfsr.v
.............\...\.......\generic_fifo_sc_a.v
.............\...\.......\generic_fifo_sc_b.v
.............\...\.......\lfsr.v
.............\...\.......\timescale.v
.............\sim
.............\...\CVS
.............\...\...\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\rtl_sim
.............\...\.......\bin
.............\...\.......\...\CVS
.............\...\.......\...\...\Entries
.............\...\.......\...\...\Repository
.............\...\.......\...\...\Root
.............\...\.......\...\Makefile
.............\...\.......\CVS
.............\...\.......\...\Entries
.............\...\.......\...\Repository
.............\...\.......\...\Root
.............\...\.......\run
.............\...\.......\...\CVS
.............\...\.......\...\...\Entries
.............\...\.......\...\...\Repository
.............\...\.......\...\...\Root
.............\...\.......\...\waves
.............\...\.......\...\.....\CVS
.............\...\.......\...\.....\...\Entries
.............\...\.......\...\.....\...\Repository
.............\...\.......\...\.....\...\Root
.............\...\.......\...\.....\waves.do
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