Description: External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
- [weifen1] - CPLD procedures, dividers
- [cpld] - a vhdl program use in my prj ,may be giv
- [bianyantiqu3.30] - Edge extractor, the falling edge of the
- [TIM_DLY_LED] - Controllable single narrow pulse signal
File list (Check if you may need any files):
COUNTER.txt