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- Other systems
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- File Size:
- 8.65mb
- Update:
- 2012-11-26
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Description: Xilinx XC4VSX35 at the core of the XtremeDSP Development Kit-IV development board of the routine, the routine testing have been successfully used in the development environment ise10.1.
File list (Check if you may need any files):
Examples
........\adc_to_dac_hookup
........\.................\adc_to_dac_hookup.bit
........\.................\ise
........\.................\...\adc_to_dac_hookup
........\.................\...\.................\adc_to_dac_hookup.dhp
........\.................\...\.................\adc_to_dac_hookup.ise
........\.................\...\.................\adc_to_dac_hookup.ise_ISE_Backup
........\.................\...\.................\adc_to_dac_hookup_xdb
........\.................\...\.................\.....................\tmp
........\.................\...\.................\automake.log
........\.................\...\.................\coregen.log
........\.................\...\.................\coregen.prj
........\.................\...\.................\_ngo
........\.................\...\.................\....\netlist.lst
........\.................\...\.................\_xmsgs
........\.................\...\.................\__projnav
........\.................\...\.................\.........\coregen.rsp
........\.................\...\.................\.........\parentEditConstraintsTextApp_tcl.rsp
........\.................\...\.................\.........\runXst_tcl.rsp
........\.................\...\.................\.........\sumrpt_tcl.rsp
........\.................\...\.................\__projnav.log
........\.................\osc_clock_2v80.bit
........\.................\Source
........\.................\......\adc2dac_hookup_4VSX35_FF668.ucf
........\.................\......\adc_to_dac_hookup.vhd
........\.................\......\counter.vhd
........\.................\......\dcm_standby.vhd
........\.................\......\ringregosc.vhd
........\chipscope_example
........\.................\automake.log
........\.................\basic_example.cpj
........\.................\chipscope_test.dhp
........\.................\chipscope_test.ise
........\.................\chipscope_test.ise_ISE_Backup
........\.................\coregen.log
........\.................\coregen.prj
........\.................\icon.arg
........\.................\icon.edn
........\.................\icon.ncf
........\.................\icon.ngo
........\.................\icon_xst_example.vhd
........\.................\icon_xst_vhdl_example.arg
........\.................\ila.arg
........\.................\ila.cdc
........\.................\ila.edn
........\.................\ila.ncf
........\.................\ila.ngo
........\.................\ila_xst_example.vhd
........\.................\ila_xst_vhdl_example.arg
........\.................\ledsnake.bit
........\.................\ledsnake.vhd
........\.................\ledsnake_4vsx35ff668.ucf
........\.................\_ngo
........\.................\....\icon.ngo
........\.................\....\ila.ngo
........\.................\....\netlist.lst
........\.................\_xmsgs
........\.................\__ISE_repository_chipscope_test.ise_.lock
........\.................\__projnav
........\.................\.........\coregen.rsp
........\.................\.........\cstest_1000.gfl
........\.................\.........\cstest_1000_flowplus.gfl
........\.................\.........\runXst_tcl.rsp
........\.................\.........\sumrpt_tcl.rsp
........\.................\__projnav.log
........\Clock_Designs
........\.............\ext_clock_2v80.bit
........\.............\Source
........\.............\......\BenADDA_IV_ClockDriver_XC2V80.ucf
........\.............\......\BenADDA_IV_ClockDriver_XC2V80_ExternalClock.ucf
........\.............\......\EXT_CLOCK.vhd
........\.............\......\OSC_CLOCK.vhd
........\edk_example
........\...........\bitinit.log
........\...........\bootloops
........\...........\.........\microblaze_0.elf
........\...........\data
........\...........\....\system.cel
........\...........\....\system.ucf
........\...........\etc
........\...........\...\bitgen.ut
........\...........\...\bitgen_spartan3.ut
........\...........\...\download.cmd
........\...........\...\fast_runtime.opt
........\...........\...\xmd_microblaze_0.opt
........\...........\hdl
........