Description: VHDL language description, the clock frequency, a given CPLD experiment board system clock set 50M, but as a result of this work, we will be the system clock frequency after 20 hours of work needed to be DS18B20 clock, about 1.25M.
File list (Check if you may need any files):
clk_div
.......\clk_div.asm.rpt
.......\clk_div.bsf
.......\clk_div.done
.......\clk_div.fit.rpt
.......\clk_div.fit.smsg
.......\clk_div.fit.summary
.......\clk_div.flow.rpt
.......\clk_div.map.rpt
.......\clk_div.map.summary
.......\clk_div.pin
.......\clk_div.pof
.......\clk_div.qpf
.......\clk_div.qsf
.......\clk_div.qws
.......\clk_div.sim.rpt
.......\clk_div.tan.rpt
.......\clk_div.tan.summary
.......\clk_div.vhd
.......\clk_div.vhd.bak
.......\clk_div.vwf
.......\db
.......\..\clk_div.asm.qmsg
.......\..\clk_div.asm_labs.ddb
.......\..\clk_div.cbx.xml
.......\..\clk_div.cmp.cdb
.......\..\clk_div.cmp.hdb
.......\..\clk_div.cmp.logdb
.......\..\clk_div.cmp.rdb
.......\..\clk_div.cmp.tdb
.......\..\clk_div.cmp0.ddb
.......\..\clk_div.dbp
.......\..\clk_div.db_info
.......\..\clk_div.eco.cdb
.......\..\clk_div.eds_overflow
.......\..\clk_div.fit.qmsg
.......\..\clk_div.hier_info
.......\..\clk_div.hif
.......\..\clk_div.map.cdb
.......\..\clk_div.map.hdb
.......\..\clk_div.map.logdb
.......\..\clk_div.map.qmsg
.......\..\clk_div.pre_map.cdb
.......\..\clk_div.pre_map.hdb
.......\..\clk_div.psp
.......\..\clk_div.pss
.......\..\clk_div.rtlv.hdb
.......\..\clk_div.rtlv_sg.cdb
.......\..\clk_div.rtlv_sg_swap.cdb
.......\..\clk_div.sgdiff.cdb
.......\..\clk_div.sgdiff.hdb
.......\..\clk_div.signalprobe.cdb
.......\..\clk_div.sim.cvwf
.......\..\clk_div.sim.hdb
.......\..\clk_div.sim.qmsg
.......\..\clk_div.sim.rdb
.......\..\clk_div.sld_design_entry.sci
.......\..\clk_div.sld_design_entry_dsc.sci
.......\..\clk_div.syn_hier_info
.......\..\clk_div.tan.qmsg
.......\..\clk_div.tis_db_list.ddb
.......\..\prev_cmp_clk_div.map.qmsg
.......\..\prev_cmp_clk_div.qmsg
.......\..\prev_cmp_clk_div.sim.qmsg
.......\..\wed.wsf
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