Description: DDS frequency synthesizer (using VHDL hardware description language, through the development of Altera QuartusII)
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程序
....\data_rom.asm.rpt
....\data_rom.cmp
....\data_rom.done
....\data_rom.fit.eqn
....\data_rom.fit.rpt
....\data_rom.fit.summary
....\data_rom.flow.rpt
....\data_rom.map.eqn
....\data_rom.map.rpt
....\data_rom.map.summary
....\data_rom.mif
....\data_rom.pin
....\data_rom.pof
....\data_rom.qpf
....\data_rom.qsf
....\data_rom.sof
....\data_rom.tan.rpt
....\data_rom.tan.summary
....\data_rom.vhd
....\db
....\..\singt.asm.qmsg
....\..\singt.cbx.xml
....\..\singt.cmp.cdb
....\..\singt.cmp.hdb
....\..\singt.cmp.logdb
....\..\singt.cmp.rdb
....\..\singt.cmp.tdb
....\..\singt.cmp0.ddb
....\..\singt.dbp
....\..\singt.db_info
....\..\singt.eco.cdb
....\..\singt.eco.cdb.wrk
....\..\singt.eds_overflow
....\..\singt.fit.qmsg
....\..\singt.hier_info
....\..\singt.hif
....\..\singt.map.cdb
....\..\singt.map.hdb
....\..\singt.map.logdb
....\..\singt.map.qmsg
....\..\singt.pre_map.cdb
....\..\singt.pre_map.hdb
....\..\singt.psp
....\..\singt.rpp.qmsg
....\..\singt.rtlv.hdb
....\..\singt.rtlv_sg.cdb
....\..\singt.rtlv_sg_swap.cdb
....\..\singt.sgate.rvd
....\..\singt.sgate_sm.rvd
....\..\singt.sgdiff.cdb
....\..\singt.sgdiff.hdb
....\..\singt.sim.hdb
....\..\singt.sim.qmsg
....\..\singt.sim.rdb
....\..\singt.sim.vwf
....\..\singt.sld_design_entry.sci
....\..\singt.sld_design_entry_dsc.sci
....\..\singt.syn_hier_info
....\..\singt.tan.qmsg
....\..\wed.zsf
....\singt.asm.rpt
....\singt.cdf
....\singt.done
....\singt.fit.eqn
....\singt.fit.rpt
....\singt.fit.summary
....\singt.flow.rpt
....\singt.map.eqn
....\singt.map.rpt
....\singt.map.summary
....\singt.pin
....\singt.pof
....\singt.qpf
....\singt.qsf
....\singt.qws
....\singt.sim.rpt
....\singt.sof
....\singt.tan.rpt
....\singt.tan.summary
....\singt.vhd
....\singt.vwf
....\singt_assignment_defaults.qdf