Description: Use Libero8.3 as the developing environment, designed a track signal frequency shift codec based on DDS
To Search:
- [DDS] - DDS-based digital phase-shifting sinusoi
- [dianyabaio] - AD0832 to do with the voltage meter accu
File list (Check if you may need any files):
程序代码
........\component
........\constraint
........\coreconsole
........\DDSv4.0.prj
........\DDSv4.0.prj.convert.8.1.bak
........\designer
........\........\impl1
........\........\.....\designer.log
........\........\.....\designer_genhdl.log
........\........\.....\Freq_Top.adb
........\........\.....\Freq_Top.dtf
........\........\.....\............\verify.log
........\........\.....\Freq_Top.ide_des
........\........\.....\Freq_Top.pdb
........\........\.....\Freq_Top.pdb.depends
........\........\.....\Freq_Top.tcl
........\........\.....\Freq_Top_1.adb
........\........\.....\Freq_Top_1.dtf
........\........\.....\..............\verify.log
........\........\.....\Freq_Top_1.ide_des
........\........\.....\Freq_Top_1.pdb
........\........\.....\Freq_Top_1.pdb.depends
........\........\.....\Freq_Top_1_fp
........\........\.....\.............\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\.............\Freq_Top_1.log
........\........\.....\.............\Freq_Top_1.pro
........\........\.....\.............\projectData
........\........\.....\.............\...........\Freq_Top_1.pdb
........\........\.....\Freq_Top_fp
........\........\.....\...........\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\...........\Freq_Top.log
........\........\.....\...........\Freq_Top.pro
........\........\.....\...........\projectData
........\........\.....\...........\...........\Freq_Top.pdb
........\........\.....\simulation
........\hdl
........\...\actram.v
........\...\basefreq.v
........\...\bfctrl.v
........\...\Clock_Gen.v
........\...\ddf.v
........\...\dds.v
........\...\ddsCordic.v
........\...\ddsHeader.h
........\...\ffd.v
........\...\kit.v
........\...\LCD_Driver.v
........\...\memWrap.v
........\...\outfreq.v
........\...\sel.v
........\...\Sel_Ctrl.v
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\smartgen
........\........\pll_1m
........\........\......\pll_1m.cxf
........\........\......\pll_1m.gen
........\........\......\pll_1m.log
........\........\......\pll_1m.v
........\........\pll_1m_work.ixf
........\........\smartgen.aws
........\stimulus
........\synthesis
........\.........\.recordref
........\.........\backup
........\.........\......\Freq_Top.srr
........\.........\......\Freq_Top_1.srr
........\.........\coreip
........\.........\Freq_Top.areasrr
........\.........\Freq_Top.edn
........\.........\Freq_Top.map
........\.........\Freq_Top.sdf
........\.........\Freq_Top.so
........\.........\Freq_Top.srd
........\.........\Freq_Top.srm
........\.........\Freq_Top.srr
........\.........\Freq_Top.srs
........\.........\Freq_Top.tlg
........\.........\Freq_Top_1.areasrr
........\.........\Freq_Top_1.edn
........\.........\Freq_Top_1.map
........\.........\Freq_Top_1.sdf
........\.........\Freq_Top_1.so
........\.........\Freq_Top_1.srd
........\.........\Freq_Top_1.srm
........\.........\Freq_Top_1.srr
........\.........\Freq_Top_1.srs
........\.........\Freq_Top_1.tlg
........\.........\Freq_Top_1_drc.rpt
........\.........\Freq_Top_1_sdc.sdc
........\.........\Freq_Top_drc.rpt
........\.........\Freq_Top_sdc.sdc
........\.........\Freq_Top_syn.prj
........\.........\run_options.txt
........\.........\stdout.log
........\.........\syntmp
........\.........\......\Freq_Top.msg