Description: This routine is an independent experiment is designed to allow you familiarize yourself with the basic syntax of VHDL language, which is relatively simple program. To achieve a clock signal clk is the frequency of the function, you can look at the waveform simulation results. Waveform simulation process can refer to video " wave simulation. Exe" file, there is a more detailed method of operation. In fact, routine project already contains a waveform simulation file, we can direct simulation, observe the results.
File list (Check if you may need any files):
example1
........\db
........\div.asm.rpt
........\div.done
........\div.fit.rpt
........\div.fit.smsg
........\div.fit.summary
........\div.flow.rpt
........\div.map.rpt
........\div.map.summary
........\div.pin
........\div.pof
........\div.qpf
........\div.qsf
........\div.qws
........\div.sim.rpt
........\div.tan.rpt
........\div.tan.summary
........\div.vhd
........\div.vwf
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