Description: moore state machine processes a total of four conditions, idle idle wait for ready signal ready to enter the state decision or sentence to wait for ready signal ruling the state decision will oe, we set the signal low, but also with read_write to determine the next state is read- read, or write state write if read_write as ' 1 ' read-read, or write state write read status will oe set high, we set low write status will oe set low, we set high.
To Search:
- [MOORE] - State machine design, using VHDL for MOO
File list (Check if you may need any files):
example2
........\db
........\..\moore.db_info
........\..\moore.eco.cdb
........\..\moore.sld_design_entry.sci
........\moore.asm.rpt
........\moore.done
........\moore.fit.rpt
........\moore.fit.smsg
........\moore.fit.summary
........\moore.flow.rpt
........\moore.map.rpt
........\moore.map.summary
........\moore.pin
........\moore.pof
........\moore.qpf
........\moore.qsf
........\moore.qws
........\moore.sim.rpt
........\moore.tan.rpt
........\moore.tan.summary
........\moore.vhd
........\moore.vwf
........\moore_assignment_defaults.qdf
Download