Description: A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules
File list (Check if you may need any files):
adder
.....\adder
.....\.....\db
.....\.....\..\full_adder.asm.qmsg
.....\.....\..\full_adder.cbx.xml
.....\.....\..\full_adder.cmp.cdb
.....\.....\..\full_adder.cmp.hdb
.....\.....\..\full_adder.cmp.logdb
.....\.....\..\full_adder.cmp.qrpt
.....\.....\..\full_adder.cmp.rdb
.....\.....\..\full_adder.cmp.tdb
.....\.....\..\full_adder.cmp0.ddb
.....\.....\..\full_adder.dbp
.....\.....\..\full_adder.db_info
.....\.....\..\full_adder.eco.cdb
.....\.....\..\full_adder.eds_overflow
.....\.....\..\full_adder.fit.qmsg
.....\.....\..\full_adder.fnsim.hdb
.....\.....\..\full_adder.fnsim.qmsg
.....\.....\..\full_adder.hier_info
.....\.....\..\full_adder.hif
.....\.....\..\full_adder.map.cdb
.....\.....\..\full_adder.map.hdb
.....\.....\..\full_adder.map.logdb
.....\.....\..\full_adder.map.qmsg
.....\.....\..\full_adder.pre_map.cdb
.....\.....\..\full_adder.pre_map.hdb
.....\.....\..\full_adder.psp
.....\.....\..\full_adder.rtlv.hdb
.....\.....\..\full_adder.rtlv_sg.cdb
.....\.....\..\full_adder.rtlv_sg_swap.cdb
.....\.....\..\full_adder.sgdiff.cdb
.....\.....\..\full_adder.sgdiff.hdb
.....\.....\..\full_adder.signalprobe.cdb
.....\.....\..\full_adder.sim.hdb
.....\.....\..\full_adder.sim.qmsg
.....\.....\..\full_adder.sim.qrpt
.....\.....\..\full_adder.sim.rdb
.....\.....\..\full_adder.sim.vwf
.....\.....\..\full_adder.sld_design_entry.sci
.....\.....\..\full_adder.sld_design_entry_dsc.sci
.....\.....\..\full_adder.syn_hier_info
.....\.....\..\full_adder.tan.qmsg
.....\.....\full_adder.asm.rpt
.....\.....\full_adder.bdf
.....\.....\full_adder.done
.....\.....\full_adder.fit.eqn
.....\.....\full_adder.fit.rpt
.....\.....\full_adder.fit.summary
.....\.....\full_adder.flow.rpt
.....\.....\full_adder.map.eqn
.....\.....\full_adder.map.rpt
.....\.....\full_adder.map.summary
.....\.....\full_adder.pin
.....\.....\full_adder.qpf
.....\.....\full_adder.qsf
.....\.....\full_adder.qws
.....\.....\full_adder.sim.rpt
.....\.....\full_adder.tan.rpt
.....\.....\full_adder.tan.summary
.....\.....\half_adder.bsf
.....\.....\half_adder.vhd
.....\.....\half_adder.vwf
.....\DE2_pin_assignments.csv
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