Description: vhdl uart lab
ENTITY uart IS
PORT ( SIGNAL clock,reset : IN STD_LOGIC
SIGNAL sdatain : IN STD_LOGIC
SIGNAL oready, sdataout : INOUT STD_LOGIC
SIGNAL iready : INOUT STD_LOGIC
SIGNAL charin : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
SIGNAL charout : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
SIGNAL write, read : INOUT STD_LOGIC
SIGNAL sdatain_out : OUT STD_LOGIC
SIGNAL sdataout_out : OUT STD_LOGIC
SIGNAL reset_out : OUT STD_LOGIC
SIGNAL sample_clock_out : OUT STD_LOGIC )
END uart
To Search:
File list (Check if you may need any files):
accuracytest.m
binsplit.m
concatenate.m
dec2twoscomp.m
fixerror.m
fixmatlab.m
float2bin.m
freq_response.m
generatecos.m
sample_proc.vhd
sendcos.m
sendwave.m
twoscomp2dec.m
uart.vhd
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