Description: State Machine also known as Finite State Machine (FSM). State Machine is a sequential circuit, the most comprehensive kind of logical methods, such as registers, shift registers, namely, number of devices covered by renewable as a function of fixed State Machine. But the State Machine is usually used in a relatively special sequential logical circuit in the manner described with the State Diagram way, is usually a more systematic approach. There了 correct Shell Condition diagram, we can design future pursuant to the State Diagram a State Machine, in order to meet the required design specifications.
- [fsm] - FSM state machine, this document provide
- [state] - under the verilog HDL Finite State Machi
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lab9\FPGA la9實驗報告.doc
....\FSM.vhd
....\Lab9-fsm_and_sequential_circuit.pdf
....\shift.vhd
lab9
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