Description: 8-channel to achieve high-speed analog data acquisition, high accuracy, using time-division multiplexing method, to avoid data transmission errors.
- [FPGA-Ethernet-video] - Introduce how to realize the network vid
- [SDH] - He is an SDH uplink code, there is compo
- [Encode] - Codec 16, time division multiplexing, a
- [FBR_TR16] - Codec 16, time division multiplexing, a
- [1] - Multi-channel signal sampling, time divi
- [F7-2VT-1DR] - 2-way video PDH' s, VHDL source code,
- [fre500000] - Such as precision digital frequency mete
- [r8_fj_noframe_bs] - Matlab simulation with eight-way time-di
- [tdm_latest[1]] - TDM, is time-division multiplexing. The
File list (Check if you may need any files):
Voltage_Comp_Verilog
....................\COMP_SM.v
....................\constraint
....................\coreconsole
....................\designer
....................\........\impl1
....................\........\.....\designer_genhdl.log
....................\........\.....\simulation
....................\........\.....\TOP_CM.tcl
....................\hdl
....................\...\COMP_SM.v
....................\...\TOP_CM.v
....................\phy_synthesis
....................\simulation
....................\..........\AB_CM_acm_ram_R0C0.mem
....................\..........\AB_CM_assc_ram_R0C0.mem
....................\..........\AB_CM_smev_ram_R0C0.mem
....................\..........\AB_CM_smtr_ram_R0C0.mem
....................\..........\meminit.dat
....................\..........\modelsim.ini
....................\..........\modelsim.ini.sav
....................\..........\modelsim.log
....................\..........\NVM_CM.mem
....................\..........\presynth
....................\..........\........\@a@b_@c@m
....................\..........\........\.........\verilog.psm
....................\..........\........\.........\_primary.dat
....................\..........\........\.........\_primary.vhd
....................\..........\........\@a@b_@c@m_assc_ram
....................\..........\........\..................\verilog.psm
....................\..........\........\..................\_primary.dat
....................\..........\........\..................\_primary.vhd
....................\..........\........\@a@b_@c@m_assc_wrapper
....................\..........\........\......................\verilog.psm
....................\..........\........\......................\_primary.dat
....................\..........\........\......................\_primary.vhd
....................\..........\........\@a@b_@c@m_smev_ram
....................\..........\........\..................\verilog.psm
....................\..........\........\..................\_primary.dat
....................\..........\........\..................\_primary.vhd
....................\..........\........\@a@b_@c@m_smev_wrapper
....................\..........\........\......................\verilog.psm
....................\..........\........\......................\_primary.dat
....................\..........\........\......................\_primary.vhd
....................\..........\........\@a@b_@c@m_smtr_ram
....................\..........\........\..................\verilog.psm
....................\..........\........\..................\_primary.dat
....................\..........\........\..................\_primary.vhd
....................\..........\........\@a@b_@c@m_smtr_wrapper
....................\..........\........\......................\verilog.psm
....................\..........\........\......................\_primary.dat
....................\..........\........\......................\_primary.vhd
....................\..........\........\@a@s@s@c
....................\..........\........\........\verilog.psm
....................\..........\........\........\_primary.dat
....................\..........\........\........\_primary.vhd
....................\..........\........\@c@o@m@p_@s@m
....................\..........\........\.............\verilog.psm
....................\..........\........\.............\_primary.dat
....................\..........\........\.............\_primary.vhd
....................\..........\........\@i@n@i@t@c@f@g
....................\..........\........\..............\verilog.psm
....................\..........\........\..............\_primary.dat
....................\..........\........\..............\_primary.vhd
....................\..........\........\@i@n@i@t@c@f@g_@x@a
....................\..........\........\...................\verilog.psm
....................\..........\........\...................\_primary.dat
....................\..........\........\...................\_primary.vhd
....................\..........\........\@i@n@i@t@c@f@g_@x@b
....................\..........\........\............
Download