UART的VHDL實現源碼
..................\UART 源碼 (Lattice Version)
..................\...........................\intface.vhd
..................\...........................\modem.vhd
..................\...........................\rxcver.vhd
..................\...........................\txmitt.vhd
..................\...........................\uart_5kvg_top.vhd
..................\...........................\uart_an_lattice.pdf
..................\...........................\uart_int_tb.vhd
..................\...........................\uart_rxerr_tb.vhd
..................\...........................\uart_rx_tb.vhd
..................\...........................\uart_top.vhd
..................\...........................\uart_tx_tb.vhd
..................\UART 源碼 (Verilog)
..................\...................\address_decode.v
..................\...................\clock_divider.v
..................\...................\control_operation.v
..................\...................\cpu_interface.v
..................\...................\serial_interface.v
..................\...................\status_registers.v
..................\...................\tester.v
..................\...................\uart_tb.v
..................\...................\uart_top.v
..................\...................\xmit_rcv_control.v
..................\UART 源碼 (VHDL)
..................\................\address_decode_rtl.vhd
..................\................\clock_divider.v
..................\................\control_operation_fsm.vhd
..................\................\cpu_interface_rtl.vhd
..................\................\serial_interface_rtl.vhd
..................\................\status_registers_rtl.vhd
..................\................\tester.v
..................\................\uart_tb.v
..................\................\uart_top_rtl.vhd
..................\................\xmit_rcv_control_fsm.vhd
..................\UART-16550
..................\..........\bench
..................\..........\.....\CVS
..................\..........\.....\...\Entries
..................\..........\.....\...\Repository
..................\..........\.....\...\Root
..................\..........\.....\verilog
..................\..........\.....\.......\CVS
..................\..........\.....\.......\...\Entries
..................\..........\.....\.......\...\Repository
..................\..........\.....\.......\...\Root
..................\..........\.....\.......\uart_test.v
..................\..........\.....\vhdl
..................\..........\.....\....\.keepme
..................\..........\.....\....\CVS
..................\..........\.....\....\...\Entries
..................\..........\.....\....\...\Repository
..................\..........\.....\....\...\Root
..................\..........\Doc
..................\..........\...\CHANGES.txt
..................\..........\...\CVS
..................\..........\...\...\Entries
..................\..........\...\...\Repository
..................\..........\...\...\Root
..................\..........\...\src
..................\..........\...\...\CVS
..................\..........\...\...\...\Entries
..................\..........\...\...\...\Repository
..................\..........\...\...\...\Root
..................\..........\...\...\UART_spec.doc
..................\..........\...\UART_spec.pdf
..................\..........\fv
..................\..........\..\.keepme
..................\..........\..\CVS
..................\..........\..\...\Entries
..................\..........\..\...\Repository
..................\..........\..\...\Root
..................\..........\lint
..................\..........\....\bin
..................\..........\....\...\.keepme
..................\..........\....\...\CVS
..................\..........\....\...\...\Entries
..................\..........\....\...\...\Repository
..................\..........\....\...\...\Root
..................\..........\....\CVS
..................\..........\....\...\Entries
..................\..........\....\...\Repository
..................\..........\