Description: VHDL language used to describe a counter, if used the package ieee.std_logic_unsigned, counters in the description of which can be used when the function "+" (count increments) and "-" (decrease count). By the assumption that the design is a counter and that counter was for the vector, then when all the spaces are' 1 ' , the counter will automatically become the next state' 0' . For example, assume that the value of counter to " 111" is to stop, then prior to the test by a counter value. If the counter has been that an integer type, there must be limits on testing. Otherwise, the count value of 7-shun, and to be implemented by 1 operation, at this time simulator will be pointed out that an error occurred
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