VHDL for the basic realization of the various circ

Title: VHDL

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2012-11-26
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Description: VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction

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[ripple-lookahead-carryselect-adder] - Ripple Adder : 16-bit full adder, semi-C
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[multiply] - Multiplier described in VHDL language. I
[OPERATION_UNIT] - The procedure for encryption chip unit i
[xiandaitongxinxitongmatlab] - The second edition of a modern communica

File list (Check if you may need any files):

VHDL
....\ALU-VHDL
....\........\ALU.done
....\........\ALU.flow.rpt
....\........\ALU.map.rpt
....\........\ALU.map.summary
....\........\ALU.qpf
....\........\ALU.qsf
....\........\ALU.qws
....\........\ALU.sim.rpt
....\........\ALU.vhd
....\........\ALU.vwf
....\........\db
....\........\..\add_sub_8rh.tdf
....\........\..\add_sub_9rh.tdf
....\........\..\add_sub_knh.tdf
....\........\..\ALU.cbx.xml
....\........\..\ALU.cmp.rdb
....\........\..\ALU.dbp
....\........\..\ALU.db_info
....\........\..\ALU.eco.cdb
....\........\..\ALU.eds_overflow
....\........\..\ALU.fnsim.cdb
....\........\..\ALU.fnsim.hdb
....\........\..\ALU.fnsim.qmsg
....\........\..\ALU.hier_info
....\........\..\ALU.hif
....\........\..\ALU.map.cdb
....\........\..\ALU.map.hdb
....\........\..\ALU.map.logdb
....\........\..\ALU.map.qmsg
....\........\..\ALU.pre_map.cdb
....\........\..\ALU.pre_map.hdb
....\........\..\ALU.psp
....\........\..\ALU.pss
....\........\..\ALU.rpp.qmsg
....\........\..\ALU.rtlv.hdb
....\........\..\ALU.rtlv_sg.cdb
....\........\..\ALU.rtlv_sg_swap.cdb
....\........\..\ALU.sgate.rvd
....\........\..\ALU.sgate_sm.rvd
....\........\..\ALU.sgdiff.cdb
....\........\..\ALU.sgdiff.hdb
....\........\..\ALU.sim.hdb
....\........\..\ALU.sim.qmsg
....\........\..\ALU.sim.rdb
....\........\..\ALU.sim.vwf
....\........\..\ALU.sld_design_entry.sci
....\........\..\ALU.sld_design_entry_dsc.sci
....\........\..\ALU.syn_hier_info
....\........\..\mux_jcc.tdf
....\........\..\wed.zsf
....\D触发器VHDL
....\...........\db
....\...........\..\dff422.cbx.xml
....\...........\..\dff422.cmp.rdb
....\...........\..\dff422.dbp
....\...........\..\dff422.db_info
....\...........\..\dff422.eco.cdb
....\...........\..\dff422.eds_overflow
....\...........\..\dff422.fnsim.cdb
....\...........\..\dff422.fnsim.hdb
....\...........\..\dff422.fnsim.qmsg
....\...........\..\dff422.hier_info
....\...........\..\dff422.hif
....\...........\..\dff422.map.cdb
....\...........\..\dff422.map.hdb
....\...........\..\dff422.map.logdb
....\...........\..\dff422.map.qmsg
....\...........\..\dff422.pre_map.cdb
....\...........\..\dff422.pre_map.hdb
....\...........\..\dff422.psp
....\...........\..\dff422.pss
....\...........\..\dff422.rpp.qmsg
....\...........\..\dff422.rtlv.hdb
....\...........\..\dff422.rtlv_sg.cdb
....\...........\..\dff422.rtlv_sg_swap.cdb
....\...........\..\dff422.sgate.rvd
....\...........\..\dff422.sgate_sm.rvd
....\...........\..\dff422.sgdiff.cdb
....\...........\..\dff422.sgdiff.hdb
....\...........\..\dff422.sim.hdb
....\...........\..\dff422.sim.qmsg
....\...........\..\dff422.sim.rdb
....\...........\..\dff422.sim.vwf
....\...........\..\dff422.sld_design_entry.sci
....\...........\..\dff422.sld_design_entry_dsc.sci
....\...........\..\dff422.syn_hier_info
....\...........\..\wed.zsf
....\...........\dff422.done
....\...........\dff422.flow.rpt
....\...........\dff422.map.rpt
....\...........\dff422.map.summary
....\...........\dff422.qpf
....\...........\dff422.qsf
....\...........\dff422.qws
....\...........\dff422.sim.rpt
....\...........\dff422.vhd
....\...........\dff422.vwf
....\串并型乘法器VHDL

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