Description: FPGA realization of the use of nuclear 51IP download and run, and downloaded to the FPGA after the nuclear 51IP to run their own procedures for the preparation of the single-chip, single-chip soft-core 51 favorable resolved, single-chip hardware of many restrictions 51 to improve the performance of a single chip.
File list (Check if you may need any files):
8051_test2
..........\8051_test.qws
..........\8051_test2.asm.rpt
..........\8051_test2.bdf
..........\8051_test2.done
..........\8051_test2.eda.rpt
..........\8051_test2.fit.rpt
..........\8051_test2.fit.smsg
..........\8051_test2.fit.summary
..........\8051_test2.flow.rpt
..........\8051_test2.map.rpt
..........\8051_test2.map.summary
..........\8051_test2.pin
..........\8051_test2.pof
..........\8051_test2.qpf
..........\8051_test2.qsf
..........\8051_test2.qws
..........\8051_test2.sof
..........\8051_test2.tan.rpt
..........\8051_test2.tan.summary
..........\8051的内核(vhdl).zip
..........\doc
..........\...\8051_overview.pdf
..........\...\comp_orig_ipcore.pdf
..........\...\mc8051_overview.pdf
..........\...\mc8051_user_guide.pdf
..........\keilc51
..........\.......\p1test
..........\.......\p1test.c
..........\.......\p1test.hex
..........\.......\p1test.lnp
..........\.......\p1test.LST
..........\.......\p1test.M51
..........\.......\p1test.OBJ
..........\.......\p1test.Opt
..........\.......\p1test.plg
..........\.......\p1test.Uv2
..........\.......\p1test_Opt.Bak
..........\.......\p1test_Uv2.Bak
..........\.......\test
..........\.......\....\test.LST
..........\.......\test.c
..........\.......\test.hex
..........\.......\test.lnp
..........\.......\test.LST
..........\.......\test.M51
..........\.......\test.OBJ
..........\.......\test.Opt
..........\.......\test.plg
..........\.......\test.Uv2
..........\.......\test_Opt.Bak
..........\.......\test_Uv2.Bak
..........\.......\time0.c
..........\.......\tmr0
..........\.......\tmr0.hex
..........\.......\tmr0.lnp
..........\.......\tmr0.M51
..........\.......\tmr0.plg
..........\mc8051_core.bsf
..........\mc8051_ram.bsf
..........\mc8051_ram.cmp
..........\mc8051_ram.vhd
..........\mc8051_ramx.bsf
..........\mc8051_ramx.cmp
..........\mc8051_ramx.vhd
..........\mc8051_ramx_waveforms.html
..........\mc8051_ram_waveforms.html
..........\mc8051_rom.bsf
..........\mc8051_rom.cmp
..........\mc8051_rom.vhd
..........\mc8051_rom_waveforms.html
..........\p1test.hex
..........\quartus_nativelink_synthesis.log
..........\setup.tcl
..........\simulation
..........\..........\modelsim
..........\..........\........\8051_test2.vho
..........\..........\........\8051_test2_modelsim.xrf
..........\..........\........\8051_test2_vhd.sdo
..........\syntmp.msg
..........\vhdl
..........\....\addsub_core_.vhd
..........\....\addsub_core_struc.vhd
..........\....\addsub_core_struc_cfg.vhd
..........\....\addsub_cy_.vhd
..........\....\addsub_cy_rtl.vhd
..........\....\addsub_cy_rtl_cfg.vhd
..........\....\addsub_ovcy_.vhd
..........\....\addsub_ovcy_rtl.vhd
..........\....\addsub_ovcy_rtl_cfg.vhd
..........\....\alucore_.vhd
..........\....\alucore_rtl.vhd
..........\....\alucore_rtl_cfg.vhd
..........\....\alumux_.vhd
..........\....\alumux_rtl.vhd
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