Description: Arithmetic logic unit, to achieve arithmetic add, subtract, plus one, minus one operation and logical AND, OR, and transmission of non-
- [achieveALUVerilogsourcecode.Rar] - achieve ALU Verilog source code, and pro
- [ALU] - Verilog prepared with 4 ALU, arithmetic
- [EWB] - This article is designed EWB program des
- [ALU] - design of alu，alu design, implement 32,
File list (Check if you may need any files):
ALU\ALU.qpf
...\ALU.qsf
...\reg.vhd
...\ALU.map.eqn
...\ALU.map.rpt
...\ALU.flow.rpt
...\ALU.map.summary
...\ALU.fit.eqn
...\ALU.pin
...\ALU.fit.rpt
...\ALU.fit.summary
...\ALU.sof
...\ALU.pof
...\ALU.asm.rpt
...\ALU.tan.summary
...\ALU.tan.rpt
...\ALU.done
...\ALU.vhd
...\ALU.qws
...\cmp_state.ini
...\db\ALU.db_info
...\..\ALU.asm.qmsg
...\..\ALU.cmp.rdb
...\..\ALU.cbx.xml
...\..\ALU_cmp.qrpt
...\..\ALU.hif
...\..\ALU.tan.qmsg
...\..\ALU.rtlv.hdb
...\..\ALU.eco.cdb
...\..\ALU.hier_info
...\..\ALU.rtlv_sg.cdb
...\..\ALU.rtlv_sg_swap.cdb
...\..\ALU.pre_map.hdb
...\..\ALU.map.qmsg
...\..\ALU.pre_map.cdb
...\..\ALU.psp
...\..\ALU.sld_design_entry.sci
...\..\ALU.sgdiff.cdb
...\..\ALU.sgdiff.hdb
...\..\ALU.syn_hier_info
...\..\ALU.sld_design_entry_dsc.sci
...\..\ALU.fit.qmsg
...\..\ALU.map.cdb
...\..\ALU.map.hdb
...\..\ALU.rpp.qmsg
...\..\ALU.cmp0.ddb
...\..\ALU.cmp.cdb
...\..\ALU.signalprobe.cdb
...\..\ALU.cmp.hdb
...\..\ALU.cmp.tdb
...\..\ALU.sgate.rvd
...\db
ALU
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