Description: Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
- [ cuart] - verilog programme of serial port
- [UART] - UART serial procedures, verilog statemen
- [RS232] - FPGA realization of RS-232 serial port t
- [uart(Verilog)] - RS232 verilog source code, if necessary
- [rs232] - dp_xiliux the CPLD Verilog design experi
- [RS232] - RS232 serial communication protocol, ver
- [RS232_pro] - RS232 verilog coding the entire parametr
- [UART] - UART simple state machine to prepare, as
- [FPGA-URAT] - FPGA and the PC serial port automaticall
- [UART] - I have written of the FPGA asynchronous
File list (Check if you may need any files):
rs232\rs232\serial.v
.....\rs232
.....\rs232_syscon.v
rs232
Download