verilogsourcecode\Example-b8-6\des.doc
.................\............\Synplify_Pro\ALU_Syn_2.prd
.................\............\............\ALU_Syn_2.prj
.................\............\............\ALU_Syn_demo.prd
.................\............\............\ALU_Syn_demo.prj
.................\............\............\ALU_Syn_demo.sdc
.................\............\............\Mix_src.prd
.................\............\............\Mix_src_vhdl.prd
.................\............\............\Mix_src_vhdl.prj
.................\............\............\Mix_src_vlog.prd
.................\............\............\Mix_src_vlog.prj
.................\............\............\MyWorkspace.prd
.................\............\............\MyWorkspace.prj
.................\............\............\source\VHDL\ALU.VHD
.................\............\............\......\....\HDL_DEMO.VHD
.................\............\............\......\verilog\ALU.V
.................\............\............\......\.......\HDL_DEMO.V
.................\............\............\......\mixed\vhdl\mux.v
.................\............\............\......\.....\....\mux21.vhd
.................\............\............\......\.....\....\reg8.v
.................\............\............\......\.....\....\rotate.v
.................\............\............\......\.....\....\top.vhd
.................\............\............\......\.....\.erilog\mux.vhd
.................\............\............\......\.....\.......\mux21.v
.................\............\............\......\.....\.......\reg8.vhd
.................\............\............\......\.....\.......\rotate.vhd
.................\............\............\......\.....\.......\top.v
.................\............\............\rev_3\.recordref
.................\............\............\.....\layer0.tlg
.................\............\............\.....\layer1.tlg
.................\............\............\.....\layer2.tlg
.................\............\............\.....\stderr.log
.................\............\............\.....\stdout.log
.................\............\............\.....\top1.fse
.................\............\............\.....\top1.srd
.................\............\............\.....\top1.srm
.................\............\............\.....\top1.srr
.................\............\............\.....\top1.srs
.................\............\............\.....\top1.sxr
.................\............\............\.....\top1.tcl
.................\............\............\.....\top1.vqm
.................\............\............\.....\top1.xrf
.................\............\............\.....\top1_cons.tcl
.................\............\............\.....\top1_rm.tcl
.................\............\............\.....\syntmp\mux.plg
.................\............\............\.....\......\rotate.plg
.................\............\............\.....\......\top.plg
.................\............\............\.....\......\top1.plg
.................\............\............\....2\.recordref
.................\............\............\.....\AutoConstraint_top.sdc
.................\............\............\.....\layer0.tlg
.................\............\............\.....\layer1.tlg
.................\............\............\.....\layer2.tlg
.................\............\............\.....\stderr.log
.................\............\............\.....\stdout.log
.................\............\............\.....\top.fse
.................\............\............\.....\top.srd
.................\............\............\.....\top.srm
.................\............\............\.....\top.srr
.................\............\............\.....\top.srs
.................\............\............\.....\top.sxr
.................\............\............\.....\top.tcl
.................\............\............\.....\top.vqm
.................\............\............\.....\top.xrf
.................\............\............\.....\top_cons.tcl
.................\............\...........