Description: D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
File list (Check if you may need any files):
trigger
.......\jk_trigger.v
.......\jk_trigger.vcd
.......\jk_trigger.v~
.......\d_trigger.v
.......\d_trigger.vcd
.......\jk_trigger.vvp
.......\d_trigger.v~
.......\d_trigger.vvp