Description: CDMA.1X, the solution of interwoven FPGA implementation, the program prepared based on VHDL, in the XILINX development board to achieve.
To Search:
- [bit_intealeaver1] - verilog HDL language dvb_t the bit inter
- [Interleave] - In Maxplus software platform developed u
- [88dianzhen] - VHDL language using 8* 8 dot matrix disp
- [soc-gr0040-010309] - xsoc vhdl verilog risc cpu soc implement
- [DVB] - DVB system, the reconciliation Interleav
- [ps2] - This procedure is based on FPGA implemen
File list (Check if you may need any files):
deinterleave\deinterleave_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl
............\................\...\...\............\.........\.......\RunOnce_tcl_StrTbl
............\................\...\...\............\.rojectNavigatorGui\GuiProjectData
............\................\...\...\............\...................\GuiProjectData_StrTbl
............\................\...\...\............\................\dpm_project_main\dpm_project_main
............\................\...\...\............\................\................\dpm_project_main_StrTbl
............\................\...\...\............\................\__stored_objects__
............\................\...\...\............\................\__stored_objects___StrTbl
............\................\...\...\............\................\__stored_object_table__
............\................\...\...\............\HierarchicalDesign\HDProject\HDProject
............\................\...\...\............\..................\.........\HDProject_StrTbl
............\................\...\...\............\..................\__stored_object_table__
............\................\...\...\..REGISTRY__\Autonym\regkeys
............\................\...\...\............\common\regkeys
............\................\...\...\............\_ProjRepoInternal_\regkeys
............\................\...\...\............\ProjectNavigator\regkeys
............\................\...\...\............\XSLTProcess\regkeys
............\................\...\...\............\bitgen\regkeys
............\................\...\...\............\cpldfit\regkeys
............\................\...\...\............\dumpngdio\regkeys
............\................\...\...\............\fuse\regkeys
............\................\...\...\............\hprep6\regkeys
............\................\...\...\............\map\regkeys
............\................\...\...\............\netgen\regkeys
............\................\...\...\............\.gc2edif\regkeys
............\................\...\...\............\...build\regkeys
............\................\...\...\............\..dbuild\regkeys
............\................\...\...\............\par\regkeys
............\................\...\...\............\runner\regkeys
............\................\...\...\............\taengine\regkeys
............\................\...\...\............\.sim\regkeys
............\................\...\...\............\.rce\regkeys
............\................\...\...\............\vhpcomp\regkeys
............\................\...\...\............\.logcomp\regkeys
............\................\...\...\............\idem\regkeys
............\................\...\...\............\xst\regkeys
............\................\...\...\............\.pwr\regkeys
............\................\...\...\............\HierarchicalDesign\HDProject\regkeys
............\................\...\...\............\..................\regkeys
............\................\...\...\............\ProjectNavigatorGui\regkeys
............\................\...\...\............\SrcCtrl\regkeys
............\................\...\...\............\.TE\regkeys
............\................\...\...\............\...\xst\regkeys
............\................\...\...\version
............\................\...\ise.lock
............\_xmsgs\xst.xmsgs
............\deinterleave.vhd
............\deinterleave.prj
............\xst\work\sub00\vhpl00.vho
............\...\....\.....\vhpl01.vho
............\...\....\hdllib.ref
............\...\....\hdpdeps.ref
............\...\dump.xst\deinterleave.prj\ntrc.scr
............\deinterleave.xst
............\deinterleave.stx
............\.lso
............\tb_deinterleave.vhd
............\pepExtractor.prj
............\deinterleave.cmd_log
............\deinterleave.syr
............\deinterleave.lso
............\deinterleave.ntrc_log
............\deinterleave.ngr
............\deinterleave.ngc
............\tb_deinterleave.udo
............\tb_deinterleave.fdo
............\tb_deinterleave_wave.fdo
............\transcript
............\work\_info
.........
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