Description: Described in detail how to design a simple 16-bit cpu. Which contains the most basic instruction from the beginning to the most complex cu controller design ideas, program. Finally the author describes some of the vhdl language usage, and gives vhdl cpu specific parts of the code to help you more deeply to learn how to design a simple cpu
- [the-design-of-16-bit-cpu] - with vhdl hardware design language of th
- [Router] - this is a java code which makes use of t
- [CPUdesign] - Computer component experiments designed
- [cpu] - 16-bit cpu design with VHDL
- [cpu] - Given instruction processor design, 16-b
File list (Check if you may need any files):
16位实验CPU设计实例介绍.doc
MyCPU\cmp_state.ini
.....\db\MyCPU.asm.qmsg
.....\..\MyCPU.cbx.xml
.....\..\MyCPU.cmp.cdb
.....\..\MyCPU.cmp.hdb
.....\..\MyCPU.cmp.rdb
.....\..\MyCPU.cmp.tdb
.....\..\MyCPU.cmp0.ddb
.....\..\MyCPU.db_info
.....\..\MyCPU.eco.cdb
.....\..\MyCPU.eda.qmsg
.....\..\MyCPU.fit.qmsg
.....\..\MyCPU.frm.hdb
.....\..\MyCPU.hier_info
.....\..\MyCPU.hif
.....\..\MyCPU.map.cdb
.....\..\MyCPU.map.hdb
.....\..\MyCPU.map.qmsg
.....\..\MyCPU.pre_map.cdb
.....\..\MyCPU.pre_map.hdb
.....\..\MyCPU.psp
.....\..\MyCPU.rpp.qmsg
.....\..\MyCPU.rtlv.hdb
.....\..\MyCPU.rtlv_sg.cdb
.....\..\MyCPU.rtlv_sg_swap.cdb
.....\..\MyCPU.sgate.rvd
.....\..\MyCPU.sgdiff.cdb
.....\..\MyCPU.sgdiff.hdb
.....\..\MyCPU.signalprobe.cdb
.....\..\MyCPU.sld_design_entry.sci
.....\..\MyCPU.sld_design_entry_dsc.sci
.....\..\MyCPU.swb.qmsg
.....\..\MyCPU.syn_hier_info
.....\..\MyCPU.tan.qmsg
.....\..\MyCPU_cmp.qrpt
.....\decoder_2_to_4.vhd
.....\decoder_unit.vhd
.....\exe_unit.vhd
.....\exp_cpu_components.vhd
.....\instru_fetch.vhd
.....\memory_unit.vhd
.....\mux_4_to_1.vhd
.....\MyCPU.asm.rpt
.....\MyCPU.cdf
.....\MyCPU.done
.....\MyCPU.eda.rpt
.....\MyCPU.fit.eqn
.....\MyCPU.fit.rpt
.....\MyCPU.fit.summary
.....\MyCPU.flow.rpt
.....\MyCPU.map.eqn
.....\MyCPU.map.rpt
.....\MyCPU.map.summary
.....\MyCPU.pin
.....\MyCPU.pof
.....\MyCPU.qpf
.....\MyCPU.qsf
.....\MyCPU.qws
.....\MyCPU.sof
.....\MyCPU.tan.rpt
.....\MyCPU.tan.summary
.....\MyCPU.vhd
.....\MyCPU.vwf
.....\reg.vhd
.....\regfile.vhd
.....\simulation\modelsim\MyCPU.vho
.....\..........\........\MyCPU_modelsim.xrf
.....\..........\........\MyCPU_vhd.sdo
.....\test1.txt
.....\.iming\primetime\MyCPU.vho
.....\......\.........\MyCPU_pt_vhd.tcl
.....\......\.........\MyCPU_vhd.sdo
.....\zha.txt
.....\simulation\modelsim
.....\timing\primetime
.....\db
.....\simulation
.....\timing
MyCPU
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