Description: Digital clock is a practical and simple for independent design, but according to different practices, changes and a lot of functions, designed to the sub-frequency digital clock, counting, state transition, binary conversion, and processing Deng special circumstances. Design should be easy to difficult, first to design a simple digital clock, and then expand the functionality. Digital clock in any case, is a separate chip, as a system, do not need, and other smart chip to communicate. This procedure mainly simple time-keeping.
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File list (Check if you may need any files):
states\db\add_sub_lnh.tdf
......\..\add_sub_pnh.tdf
......\..\mux_19c.tdf
......\..\states.analyze_file.qmsg
......\..\states.asm.qmsg
......\..\states.cbx.xml
......\..\states.cmp.cdb
......\..\states.cmp.hdb
......\..\states.cmp.qrpt
......\..\states.cmp.rdb
......\..\states.cmp.tdb
......\..\states.cmp0.ddb
......\..\states.dbp
......\..\states.db_info
......\..\states.eco.cdb
......\..\states.eds_overflow
......\..\states.fit.qmsg
......\..\states.fnsim.cdb
......\..\states.fnsim.hdb
......\..\states.fnsim.qmsg
......\..\states.hier_info
......\..\states.hif
......\..\states.map.cdb
......\..\states.map.hdb
......\..\states.map.qmsg
......\..\states.pre_map.cdb
......\..\states.pre_map.hdb
......\..\states.psp
......\..\states.rtlv.hdb
......\..\states.rtlv_sg.cdb
......\..\states.rtlv_sg_swap.cdb
......\..\states.sgdiff.cdb
......\..\states.sgdiff.hdb
......\..\states.sim.hdb
......\..\states.sim.qmsg
......\..\states.sim.qrpt
......\..\states.sim.rdb
......\..\states.sim.vwf
......\..\states.sld_design_entry.sci
......\..\states.sld_design_entry_dsc.sci
......\..\states.syn_hier_info
......\..\states.tan.qmsg
......\states.asm.rpt
......\states.done
......\states.fit.eqn
......\states.fit.rpt
......\states.fit.summary
......\states.flow.rpt
......\states.map.eqn
......\states.map.rpt
......\states.map.summary
......\states.pin
......\states.pof
......\states.qpf
......\states.qsf
......\states.qws
......\states.sim.rpt
......\states.tan.rpt
......\states.tan.summary
......\states.vhd
......\states07022021.vwf
......\talkback\states.asm.talkback.xml
......\........\states.fit.talkback.xml
......\........\states.map.talkback.xml
......\........\states.sim.talkback.xml
......\........\states.tan.talkback.xml
......\db
......\talkback
states
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