Description: Verilog in quartus II, prepared under the stepper motor with position control program, which contains seven sub-modules, and a top-level module, the program-level clarity, function clear. Is a personal collection, recommend you to download to learn!
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bujindianjikongzhi\fdiv\fdiv.qpf
..................\....\fdiv.qsf
..................\....\db\fdiv.db_info
..................\....\..\fdiv.fit.qmsg
..................\....\..\fdiv.asm.qmsg
..................\....\..\fdiv.sld_design_entry.sci
..................\....\..\fdiv.map.hdb
..................\....\..\fdiv.map.qmsg
..................\....\..\fdiv.rtlv.hdb
..................\....\..\fdiv.eco.cdb
..................\....\..\fdiv.pre_map.hdb
..................\....\..\fdiv.pre_map.cdb
..................\....\..\fdiv.map.cdb
..................\....\..\fdiv_cmp.qrpt
..................\....\..\fdiv.tan.qmsg
..................\....\..\fdiv.sim.qmsg
..................\....\..\fdiv.rtlv_sg.cdb
..................\....\..\fdiv.rtlv_sg_swap.cdb
..................\....\..\fdiv.sim.vwf
..................\....\..\fdiv.cmp.rdb
..................\....\..\fdiv.cmp.cdb
..................\....\..\fdiv.hif
..................\....\..\fdiv.cmp.hdb
..................\....\..\fdiv.hier_info
..................\....\..\fdiv.sgdiff.cdb
..................\....\..\fdiv.sgdiff.hdb
..................\....\..\fdiv.sld_design_entry_dsc.sci
..................\....\..\fdiv.psp
..................\....\..\fdiv.sim.hdb
..................\....\..\fdiv.cmp.ddb
..................\....\..\fdiv.sim.rdb
..................\....\..\fdiv.syn_hier_info
..................\....\..\fdiv.cmp.tdb
..................\....\..\fdiv.cmp0.ddb
..................\....\..\fdiv.eds_overflow
..................\....\..\fdiv_sim.qrpt
..................\....\fdiv.map.rpt
..................\....\fdiv.flow.rpt
..................\....\fdiv.map.summary
..................\....\fdiv.map.eqn
..................\....\fdiv.fit.eqn
..................\....\fdiv.pin
..................\....\fdiv.fit.rpt
..................\....\fdiv.fit.summary
..................\....\fdiv.pof
..................\....\fdiv.asm.rpt
..................\....\fdiv.tan.rpt
..................\....\fdiv.done
..................\....\fdiv.vwf
..................\....\fdiv.sim.rpt
..................\....\fdiv.tan.summary
..................\....\fdiv.qws
..................\....\cmp_state.ini
..................\....\fdiv.v
..................\....\fdiv.bsf
..................\counter_16_bits\counter_16_bits.qpf
..................\...............\counter_16_bits.qsf
..................\...............\db\counter_16_bits.db_info
..................\...............\..\counter_16_bits.hif
..................\...............\..\counter_16_bits.hier_info
..................\...............\..\counter_16_bits.rtlv_sg.cdb
..................\...............\..\counter_16_bits.rtlv.hdb
..................\...............\..\counter_16_bits.rtlv_sg_swap.cdb
..................\...............\..\counter_16_bits.pre_map.hdb
..................\...............\..\counter_16_bits.pre_map.cdb
..................\...............\..\counter_16_bits.psp
..................\...............\..\counter_16_bits.sgdiff.cdb
..................\...............\..\counter_16_bits.sgdiff.hdb
..................\...............\..\counter_16_bits.sld_design_entry_dsc.sci
..................\...............\..\counter_16_bits.syn_hier_info
..................\...............\..\counter_16_bits.map.cdb
..................\...............\..\counter_16_bits.map.hdb
..................\...............\..\counter_16_bits_cmp.qrpt
..................\...............\..\counter_16_bits.fit.qmsg
..................\...............\..\counter_16_bits.asm.qmsg
..................\...............\..\counter_16_bits.tan.qmsg
..................\...............\..\counter_16_bits.cmp.tdb
..................\...............\..\counter_16_bits.cmp0.ddb
..................\...............\..\counter_16_bits.cmp.cdb
..................\...............\..\counter_16_bits.cmp.hdb
..................\...............\..\counter_16_bits.cmp.rdb
..................\...............\..\counter_16_bits_sim.qrpt
..................\...............\..\counter_16_bits.sim.qmsg
..................\...............\..\counter_16_bits.sim.hdb
..................\...............\..\counter_16_bits.cmp.ddb
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