Description: Core of the system completed the circuit from the FPGA, the design selected Altera' s EPlKl00QC208-3 chip design using VHDL language to it, to achieve 8-bit digital frequency measurement
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8位数字频率计\cnt10.vhd
.............\divfre.vhd
.............\frequnce.vhd
.............\tb_cnt10.vhd
.............\tb_divfre.vhd
.............\test.vhd
.............\transcript
.............\ttt.cr.mti
.............\ttt.mpf
.............\vsim.wlf
.............\work\cnt10\behav.asm
.............\....\.....\behav.dat
.............\....\.....\_primary.dat
.............\....\display\behav.asm
.............\....\.......\behav.dat
.............\....\.......\_primary.dat
.............\....\..vfre\behav.asm
.............\....\......\behav.dat
.............\....\......\_primary.dat
.............\....\frequnce\behav.asm
.............\....\........\behav.dat
.............\....\........\_primary.dat
.............\....\reg32b\behav.asm
.............\....\......\behav.dat
.............\....\......\_primary.dat
.............\....\select8_1\behav.asm
.............\....\.........\behav.dat
.............\....\.........\_primary.dat
.............\....\tb_cnt10\behav.asm
.............\....\........\behav.dat
.............\....\........\_primary.dat
.............\....\...divfre\behav.asm
.............\....\.........\behav.dat
.............\....\.........\_primary.dat
.............\....\.est\behav.asm
.............\....\....\behav.dat
.............\....\....\_primary.dat
.............\....\....ctl\behav.asm
.............\....\.......\behav.dat
.............\....\.......\_primary.dat
.............\....\_info
.............\....\cnt10
.............\....\display
.............\....\divfre
.............\....\frequnce
.............\....\reg32b
.............\....\select8_1
.............\....\tb_cnt10
.............\....\tb_divfre
.............\....\test
.............\....\testctl
.............\work
8位数字频率计
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