Welcome!
[Sign In]
!
[Sign Up]
!
Front-page it
|
Collect it
| [
中国-简体中文
]
CodeBus
codebus.net
Hot search:
Source
embeded
web
remote control
p2p
game
More...
FAQ
Fav
Home
SourceCode
Web Code
Develop Tools
Document
E-Books
Other Resource
Get Coins
Member
Location:
Downloads
SourceCode
Embeded-SCM Develop
VHDL-FPGA-Verilog
Title:
fenpin
Download
Category:
VHDL-FPGA-Verilog
Tags:
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
hdy2003
Description:
Clock divider, beginners can download the study results were quite good
Downloaders recently:
[
More information of uploader hdy2003
]
To Search:
[
E1_DCR
] - 2MHz data clock recovery circuit, includ
[
Frequency_divider
] - With VERILOG HDL realize arbitrary frequ
File list
(Check if you may need any files):
时钟分频器\frediv9.vhd ..........\fredivn.vhd ..........\fredivn1.vhd ..........\PULSE.vhd 时钟分频器
Main Category
SourceCode
Web Code
Develop Tools
Document
Other resource
Category
About site
Total codes:
120
M
Total size:
1500
GB
Today updated:368
Members:1688565
Today members:634
Total members:198568
Downloaded:1200M
Sign UP
Help
Support
What's CodeBus
SiteMap
Contact us
CodeBus www.codebus.net
“CodeBus” is the largest source code store in internet!
1999-2018
CodeBus
All Rights Reserved.