Description: A few of their own design VHDL procedures, including the decoder circuit, multiple switches, comparator applications, and 16 by 8RAM circuit, each module and final top-level schematic and pins I have been to the good hope of learning to everyone help
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File list (Check if you may need any files):
vhdl test\bijiao\bijiao.asm.rpt
.........\......\bijiao.bdf
.........\......\bijiao.done
.........\......\bijiao.fit.eqn
.........\......\bijiao.fit.rpt
.........\......\bijiao.fit.summary
.........\......\bijiao.flow.rpt
.........\......\bijiao.map.eqn
.........\......\bijiao.map.rpt
.........\......\bijiao.map.summary
.........\......\bijiao.pin
.........\......\bijiao.pof
.........\......\bijiao.qpf
.........\......\bijiao.qsf
.........\......\bijiao.qws
.........\......\bijiao.sof
.........\......\bijiao.tan.rpt
.........\......\bijiao.tan.summary
.........\......\choose.vhd
.........\......\com.vhd
.........\......\db\bijiao.asm.qmsg
.........\......\..\bijiao.cbx.xml
.........\......\..\bijiao.cmp.cdb
.........\......\..\bijiao.cmp.hdb
.........\......\..\bijiao.cmp.qrpt
.........\......\..\bijiao.cmp.rdb
.........\......\..\bijiao.cmp.tdb
.........\......\..\bijiao.cmp0.ddb
.........\......\..\bijiao.dbp
.........\......\..\bijiao.db_info
.........\......\..\bijiao.eco.cdb
.........\......\..\bijiao.fit.qmsg
.........\......\..\bijiao.hier_info
.........\......\..\bijiao.hif
.........\......\..\bijiao.map.cdb
.........\......\..\bijiao.map.hdb
.........\......\..\bijiao.map.qmsg
.........\......\..\bijiao.pre_map.cdb
.........\......\..\bijiao.pre_map.hdb
.........\......\..\bijiao.psp
.........\......\..\bijiao.rtlv.hdb
.........\......\..\bijiao.rtlv_sg.cdb
.........\......\..\bijiao.rtlv_sg_swap.cdb
.........\......\..\bijiao.sgdiff.cdb
.........\......\..\bijiao.sgdiff.hdb
.........\......\..\bijiao.signalprobe.cdb
.........\......\..\bijiao.sld_design_entry.sci
.........\......\..\bijiao.sld_design_entry_dsc.sci
.........\......\..\bijiao.syn_hier_info
.........\......\..\bijiao.tan.qmsg
.........\......\HEX.vhd
.........\......\SEVEN.vhd
.........\......\yima.bsf
.........\......\yima.vhd
.........\choose\choose.asm.rpt
.........\......\choose.bdf
.........\......\choose.cdf
.........\......\choose.done
.........\......\choose.fit.eqn
.........\......\choose.fit.rpt
.........\......\choose.fit.summary
.........\......\choose.flow.rpt
.........\......\choose.map.eqn
.........\......\choose.map.rpt
.........\......\choose.map.summary
.........\......\choose.pin
.........\......\choose.pof
.........\......\choose.qpf
.........\......\choose.qsf
.........\......\choose.qws
.........\......\choose.sof
.........\......\choose.tan.rpt
.........\......\choose.tan.summary
.........\......\db\choose.asm.qmsg
.........\......\..\choose.cbx.xml
.........\......\..\choose.cmp.cdb
.........\......\..\choose.cmp.hdb
.........\......\..\choose.cmp.qrpt
.........\......\..\choose.cmp.rdb
.........\......\..\choose.cmp.tdb
.........\......\..\choose.cmp0.ddb
.........\......\..\choose.dbp
.........\......\..\choose.db_info
.........\......\..\choose.eco.cdb
.........\......\..\choose.fit.qmsg
.........\......\..\choose.hier_info
.........\......\..\choose.hif
.........\......\..\choose.map.cdb
.........\......\..\choose.map.hdb
.........\......\..\choose.map.qmsg
.........\......\..\choose.pre_map.cdb
.........\......\..\choose.pre_map.hdb
.........\......\..\choose.psp
.........\......\..\choose.rtlv.hdb
.........\......\..\choose.rtlv_sg.cdb
.........\......\..\choose.rtlv_sg_swap.cdb
.........\......\..\choose.sgdiff.cdb
.........\......\..\choose.sgdiff.hdb
.........\......\..\choose.signalprobe.cdb
.........\......\..\choose.sld_design_entry.sci
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